[PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform

[PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform

[dinguyen-EIB2kfCEclfQT0dZR+AlfA]

From: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>

The STMMAC Ethernet controller in SOCFPGA requires setting a register for
the phy-mode that is outside of the ethernet IP. This register resides in
the System Manager block. So we define a new DTS binding
"altr,sysmgr-phy-mask". This binding's property is a bitmask that can be
used to set the correct register bit.

Signed-off-by: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
Cc: Pavel Machek <pavel-ynQEQJNshbs@public.gmane.org>
CC: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
CC: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
CC: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
---
 .../bindings/net/stmmac-altr-socfpga.txt           |   43 ++++++++++++++++++++
 arch/arm/boot/dts/socfpga_cyclone5.dts             |   19 +++++++++
 2 files changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt

diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt
new file mode 100644
index 0000000..f0fa56a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt
@@ -0,0 +1,43 @@
+* Altera SOCFPGA specific extensions to the STMicroelectronics
+	10/100/1000 Ethernet driver (GMAC)
+
+This file documents an additional property that is required for the Altera
+SOCFPGA implementation of the STMMAC Ethernet driver. Please refer to the core
+properties of the STMMAC driver as documented in stmmac.txt.
+
+Required Properties:
+
+* compatible: should be
+	- "altr,socfpga-stmmac": for controllers with Altera SOCFPGA specific
+		extensions.
+
+* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to
+	set the appropriate register bits for the phy-mode in the System Manager.
+	The value should be:
+		-Ethernet Controller 1 (gmac0) = 0x3
+		-Ethernet Controller 2 (gmac1) = 0xC
+
+Example:
+
+	gmac0: ethernet@ff700000 {
+		compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+		reg = <0xff700000 0x2000>;
+		interrupts = <0 115 4>;
+		interrupt-names = "macirq"";
+		mac-address = [000000000000]; /* Filled in by U-Boot */
+		phy-mode = "gmii";
+
+		/* PHY Skew settings */
+		rxd0-skew-ps = <0>;
+		rxd0-skew-ps = <0>;
+		rxd1-skew-ps = <0>;
+		rxd2-skew-ps = <0>;
+		rxd3-skew-ps = <0>;
+		txen-skew-ps = <0>;
+		txc-skew-ps = <2600>;
+		rxdv-skew-ps = <0>;
+		rxc-skew-ps = <2000>;
+
+		altr,sysmgr-phy-mask = <0x3>;
+		status = "okay";
+        };
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index bfed066..44db0e6 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -95,3 +95,22 @@
 		};
 	};
 };
+
+&gmac1 {
+	phy-mode = "rgmii";
+	snps,phy-addr = <0xffffffff>; /* probe for phy addr */
+
+	rxd0-skew-ps = <0>;
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <2600>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <2000>;
+
+	altr,sysmgr-phy-mask = <0xC>;
+	status = "okay";
+};
+
-- 
1.7.9.5


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[PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

The STMMAC Ethernet controller in SOCFPGA requires setting a register for
the phy-mode that is outside of the ethernet IP. This register resides in
the System Manager block. So we define a new DTS binding
"altr,sysmgr-phy-mask". This binding's property is a bitmask that can be
used to set the correct register bit.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: devicetree at vger.kernel.org
CC: linux-arm-kernel at lists.infradead.org
---
 .../bindings/net/stmmac-altr-socfpga.txt           |   43 ++++++++++++++++++++
 arch/arm/boot/dts/socfpga_cyclone5.dts             |   19 +++++++++
 2 files changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt

diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt
new file mode 100644
index 0000000..f0fa56a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt
@@ -0,0 +1,43 @@
+* Altera SOCFPGA specific extensions to the STMicroelectronics
+	10/100/1000 Ethernet driver (GMAC)
+
+This file documents an additional property that is required for the Altera
+SOCFPGA implementation of the STMMAC Ethernet driver. Please refer to the core
+properties of the STMMAC driver as documented in stmmac.txt.
+
+Required Properties:
+
+* compatible: should be
+	- "altr,socfpga-stmmac": for controllers with Altera SOCFPGA specific
+		extensions.
+
+* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to
+	set the appropriate register bits for the phy-mode in the System Manager.
+	The value should be:
+		-Ethernet Controller 1 (gmac0) = 0x3
+		-Ethernet Controller 2 (gmac1) = 0xC
+
+Example:
+
+	gmac0: ethernet at ff700000 {
+		compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+		reg = <0xff700000 0x2000>;
+		interrupts = <0 115 4>;
+		interrupt-names = "macirq"";
+		mac-address = [000000000000]; /* Filled in by U-Boot */
+		phy-mode = "gmii";
+
+		/* PHY Skew settings */
+		rxd0-skew-ps = <0>;
+		rxd0-skew-ps = <0>;
+		rxd1-skew-ps = <0>;
+		rxd2-skew-ps = <0>;
+		rxd3-skew-ps = <0>;
+		txen-skew-ps = <0>;
+		txc-skew-ps = <2600>;
+		rxdv-skew-ps = <0>;
+		rxc-skew-ps = <2000>;
+
+		altr,sysmgr-phy-mask = <0x3>;
+		status = "okay";
+        };
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index bfed066..44db0e6 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -95,3 +95,22 @@
 		};
 	};
 };
+
+&gmac1 {
+	phy-mode = "rgmii";
+	snps,phy-addr = <0xffffffff>; /* probe for phy addr */
+
+	rxd0-skew-ps = <0>;
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <2600>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <2000>;
+
+	altr,sysmgr-phy-mask = <0xC>;
+	status = "okay";
+};
+
-- 
1.7.9.5

[PATCH 2/2] arm: socfpga: Add platform initialization for ethernet

[dinguyen-EIB2kfCEclfQT0dZR+AlfA]

From: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>

In order to correctly enable ethernet support on SOCFGPA, a couple of
platform specific initializations steps must be done.

1) Use the phy-mode DTS property to set the appropriate bits in a system
manager register.

2) The ethernet IP should only be brought out of reset when initialized.

Signed-off-by: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
Cc: Pavel Machek <pavel-ynQEQJNshbs@public.gmane.org>
CC: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
CC: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
CC: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
---
 arch/arm/mach-socfpga/core.h    |    9 +++++
 arch/arm/mach-socfpga/socfpga.c |   72 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 80 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index b05fa6a..474582b 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -28,6 +28,15 @@
 #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
 #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
 
+/* Peripheral Module Reset Register bits */
+#define RSTMGR_PERMODRST_EMAC0  0x1
+#define RSTMGR_PERMODRST_EMAC1  0x2
+
+#define SYSMGR_EMACGRP_CTRL_OFFSET 0x60
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+
 extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index bfce964..fe97423 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -19,7 +19,10 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/of_net.h>
+#include <linux/phy.h>
 #include <linux/reboot.h>
+#include <linux/stmmac.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -33,6 +36,24 @@ void __iomem *rst_manager_base_addr;
 void __iomem *clk_mgr_base_addr;
 unsigned long cpu1start_addr;
 
+static int stmmac_plat_init(struct platform_device *pdev);
+
+static struct plat_stmmacenet_data stmmacenet0_data = {
+	.init = &stmmac_plat_init,
+	.bus_id = 0,
+};
+
+static struct plat_stmmacenet_data stmmacenet1_data = {
+	.init = &stmmac_plat_init,
+	.bus_id = 1,
+};
+
+static const struct of_dev_auxdata socfpga_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff700000, NULL, &stmmacenet0_data),
+	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff702000, NULL, &stmmacenet1_data),
+	{ /* sentinel */ }
+};
+
 static struct map_desc scu_io_desc __initdata = {
 	.virtual	= SOCFPGA_SCU_VIRT_BASE,
 	.pfn		= 0, /* run-time */
@@ -47,6 +68,54 @@ static struct map_desc uart_io_desc __initdata = {
 	.type		= MT_DEVICE,
 };
 
+static int stmmac_plat_init(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	u32 ctrl, val;
+	u32 rstmask, sysmgr_phymask;
+	int phymode;
+
+	if (of_machine_is_compatible("altr,socfpga-vt"))
+		return 0;
+
+	phymode = of_get_phy_mode(np);
+	if (of_property_read_u32(np, "altr,sysmgr-phy-mask", &sysmgr_phymask))
+		pr_err("GMAC: No altr,sysmgr-phy-mask property found!\n");
+
+	switch (phymode) {
+	case PHY_INTERFACE_MODE_RGMII:
+		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+		break;
+	case PHY_INTERFACE_MODE_MII:
+	case PHY_INTERFACE_MODE_GMII:
+		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+		break;
+	default:
+		pr_err("%s bad phy mode %d", __func__, phymode);
+		return -EINVAL;
+	}
+
+	if (sysmgr_phymask == 0xC) {
+		/* gmac1 */
+		val |= (val << 2);
+		rstmask = RSTMGR_PERMODRST_EMAC1;
+	} else
+		rstmask = RSTMGR_PERMODRST_EMAC0;
+
+	/* Set the PHY mode in the system manager.*/
+	ctrl = readl(sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET);
+	ctrl &= ~sysmgr_phymask;
+	ctrl |= val;
+	writel(ctrl, (sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET));
+
+	/* Bring the appropriate ethernet ip out of reset.*/
+	ctrl = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST);
+	ctrl &= ~rstmask;
+	writel(ctrl, rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST);
+
+	return 0;
+}
+
 static void __init socfpga_scu_map_io(void)
 {
 	unsigned long base;
@@ -106,7 +175,8 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 static void __init socfpga_cyclone5_init(void)
 {
 	l2x0_of_init(0, ~0UL);
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table,
+		socfpga_auxdata_lookup, NULL);
 	of_clk_init(NULL);
 	socfpga_init_clocks();
 }
-- 
1.7.9.5


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[PATCH 2/2] arm: socfpga: Add platform initialization for ethernet

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

In order to correctly enable ethernet support on SOCFGPA, a couple of
platform specific initializations steps must be done.

1) Use the phy-mode DTS property to set the appropriate bits in a system
manager register.

2) The ethernet IP should only be brought out of reset when initialized.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: devicetree at vger.kernel.org
CC: linux-arm-kernel at lists.infradead.org
---
 arch/arm/mach-socfpga/core.h    |    9 +++++
 arch/arm/mach-socfpga/socfpga.c |   72 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 80 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index b05fa6a..474582b 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -28,6 +28,15 @@
 #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
 #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
 
+/* Peripheral Module Reset Register bits */
+#define RSTMGR_PERMODRST_EMAC0  0x1
+#define RSTMGR_PERMODRST_EMAC1  0x2
+
+#define SYSMGR_EMACGRP_CTRL_OFFSET 0x60
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+
 extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index bfce964..fe97423 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -19,7 +19,10 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/of_net.h>
+#include <linux/phy.h>
 #include <linux/reboot.h>
+#include <linux/stmmac.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -33,6 +36,24 @@ void __iomem *rst_manager_base_addr;
 void __iomem *clk_mgr_base_addr;
 unsigned long cpu1start_addr;
 
+static int stmmac_plat_init(struct platform_device *pdev);
+
+static struct plat_stmmacenet_data stmmacenet0_data = {
+	.init = &stmmac_plat_init,
+	.bus_id = 0,
+};
+
+static struct plat_stmmacenet_data stmmacenet1_data = {
+	.init = &stmmac_plat_init,
+	.bus_id = 1,
+};
+
+static const struct of_dev_auxdata socfpga_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff700000, NULL, &stmmacenet0_data),
+	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff702000, NULL, &stmmacenet1_data),
+	{ /* sentinel */ }
+};
+
 static struct map_desc scu_io_desc __initdata = {
 	.virtual	= SOCFPGA_SCU_VIRT_BASE,
 	.pfn		= 0, /* run-time */
@@ -47,6 +68,54 @@ static struct map_desc uart_io_desc __initdata = {
 	.type		= MT_DEVICE,
 };
 
+static int stmmac_plat_init(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	u32 ctrl, val;
+	u32 rstmask, sysmgr_phymask;
+	int phymode;
+
+	if (of_machine_is_compatible("altr,socfpga-vt"))
+		return 0;
+
+	phymode = of_get_phy_mode(np);
+	if (of_property_read_u32(np, "altr,sysmgr-phy-mask", &sysmgr_phymask))
+		pr_err("GMAC: No altr,sysmgr-phy-mask property found!\n");
+
+	switch (phymode) {
+	case PHY_INTERFACE_MODE_RGMII:
+		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+		break;
+	case PHY_INTERFACE_MODE_MII:
+	case PHY_INTERFACE_MODE_GMII:
+		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+		break;
+	default:
+		pr_err("%s bad phy mode %d", __func__, phymode);
+		return -EINVAL;
+	}
+
+	if (sysmgr_phymask == 0xC) {
+		/* gmac1 */
+		val |= (val << 2);
+		rstmask = RSTMGR_PERMODRST_EMAC1;
+	} else
+		rstmask = RSTMGR_PERMODRST_EMAC0;
+
+	/* Set the PHY mode in the system manager.*/
+	ctrl = readl(sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET);
+	ctrl &= ~sysmgr_phymask;
+	ctrl |= val;
+	writel(ctrl, (sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET));
+
+	/* Bring the appropriate ethernet ip out of reset.*/
+	ctrl = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST);
+	ctrl &= ~rstmask;
+	writel(ctrl, rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST);
+
+	return 0;
+}
+
 static void __init socfpga_scu_map_io(void)
 {
 	unsigned long base;
@@ -106,7 +175,8 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 static void __init socfpga_cyclone5_init(void)
 {
 	l2x0_of_init(0, ~0UL);
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table,
+		socfpga_auxdata_lookup, NULL);
 	of_clk_init(NULL);
 	socfpga_init_clocks();
 }
-- 
1.7.9.5

Re: [PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform

[Stephen Warren]

On 09/24/2013 03:11 PM, dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org wrote:
> From: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
> 
> The STMMAC Ethernet controller in SOCFPGA requires setting a register for
> the phy-mode that is outside of the ethernet IP. This register resides in
> the System Manager block. So we define a new DTS binding
> "altr,sysmgr-phy-mask". This binding's property is a bitmask that can be
> used to set the correct register bit.

> diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt

> +* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to
> +	set the appropriate register bits for the phy-mode in the System Manager.
> +	The value should be:
> +		-Ethernet Controller 1 (gmac0) = 0x3
> +		-Ethernet Controller 2 (gmac1) = 0xC

Wouldn't you need a phandle to the sysmgr node so that the driver could
be located, and a register number within its register block too? Or,
does sysmgr know which register to poke? If so, couldn't the API take
just a device index rather than a bitmask instead, and calculate the
mask itself?
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[PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform

[Stephen Warren]

On 09/24/2013 03:11 PM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> The STMMAC Ethernet controller in SOCFPGA requires setting a register for
> the phy-mode that is outside of the ethernet IP. This register resides in
> the System Manager block. So we define a new DTS binding
> "altr,sysmgr-phy-mask". This binding's property is a bitmask that can be
> used to set the correct register bit.

> diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt

> +* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to
> +	set the appropriate register bits for the phy-mode in the System Manager.
> +	The value should be:
> +		-Ethernet Controller 1 (gmac0) = 0x3
> +		-Ethernet Controller 2 (gmac1) = 0xC

Wouldn't you need a phandle to the sysmgr node so that the driver could
be located, and a register number within its register block too? Or,
does sysmgr know which register to poke? If so, couldn't the API take
just a device index rather than a bitmask instead, and calculate the
mask itself?

Re: [PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform

[Dinh Nguyen]

Hi Stephen,

On 9/26/13 6:21 PM, Stephen Warren wrote:
> On 09/24/2013 03:11 PM, dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org wrote:
>> From: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
>>
>> The STMMAC Ethernet controller in SOCFPGA requires setting a register for
>> the phy-mode that is outside of the ethernet IP. This register resides in
>> the System Manager block. So we define a new DTS binding
>> "altr,sysmgr-phy-mask". This binding's property is a bitmask that can be
>> used to set the correct register bit.
>> diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt
>> +* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to
>> +	set the appropriate register bits for the phy-mode in the System Manager.
>> +	The value should be:
>> +		-Ethernet Controller 1 (gmac0) = 0x3
>> +		-Ethernet Controller 2 (gmac1) = 0xC
> Wouldn't you need a phandle to the sysmgr node so that the driver could
> be located, and a register number within its register block too? Or,
> does sysmgr know which register to poke? If so, couldn't the API take
> just a device index rather than a bitmask instead, and calculate the
> mask itself?
The function that pokes this register is a platform specific init 
function call from the driver, so the function knows which register in 
the the sysmgr to poke. The first byte of the register has controls for 
both ethernet controllers. I thought it would be better to use a mask to 
be used to differentiate between each controller.

Thanks,
Dinh
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[PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform

[Dinh Nguyen]

Hi Stephen,

On 9/26/13 6:21 PM, Stephen Warren wrote:
> On 09/24/2013 03:11 PM, dinguyen at altera.com wrote:
>> From: Dinh Nguyen <dinguyen@altera.com>
>>
>> The STMMAC Ethernet controller in SOCFPGA requires setting a register for
>> the phy-mode that is outside of the ethernet IP. This register resides in
>> the System Manager block. So we define a new DTS binding
>> "altr,sysmgr-phy-mask". This binding's property is a bitmask that can be
>> used to set the correct register bit.
>> diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt
>> +* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to
>> +	set the appropriate register bits for the phy-mode in the System Manager.
>> +	The value should be:
>> +		-Ethernet Controller 1 (gmac0) = 0x3
>> +		-Ethernet Controller 2 (gmac1) = 0xC
> Wouldn't you need a phandle to the sysmgr node so that the driver could
> be located, and a register number within its register block too? Or,
> does sysmgr know which register to poke? If so, couldn't the API take
> just a device index rather than a bitmask instead, and calculate the
> mask itself?
The function that pokes this register is a platform specific init 
function call from the driver, so the function knows which register in 
the the sysmgr to poke. The first byte of the register has controls for 
both ethernet controllers. I thought it would be better to use a mask to 
be used to differentiate between each controller.

Thanks,
Dinh