From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sourav Poddar Date: Mon, 7 Oct 2013 15:53:00 +0530 Subject: [U-Boot] [UBOOT][PATCHv6 2/6] armv7: hw_data: change clock divider setting. In-Reply-To: <1381141384-32706-1-git-send-email-sourav.poddar@ti.com> References: <1381141384-32706-1-git-send-email-sourav.poddar@ti.com> Message-ID: <1381141384-32706-3-git-send-email-sourav.poddar@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar --- arch/arm/cpu/armv7/omap5/hw_data.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index c00bfb8..a1b249e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -170,7 +170,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ - {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ + {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */ {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ -- 1.7.1