From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754622Ab3KCU7L (ORCPT ); Sun, 3 Nov 2013 15:59:11 -0500 Received: from gate.crashing.org ([63.228.1.57]:43651 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754505Ab3KCU7J (ORCPT ); Sun, 3 Nov 2013 15:59:09 -0500 Message-ID: <1383512261.4776.21.camel@pasglop> Subject: Re: perf events ring buffer memory barrier on powerpc From: Benjamin Herrenschmidt To: Victor Kaplansky Cc: David Laight , Michael Neuling , Mathieu Desnoyers , Peter Zijlstra , Frederic Weisbecker , LKML , Oleg Nesterov , Linux PPC dev , Anton Blanchard , paulmck@linux.vnet.ibm.com Date: Mon, 04 Nov 2013 07:57:41 +1100 In-Reply-To: References: <20131028132634.GO19466@laptop.lan> <20131028163418.GD4126@linux.vnet.ibm.com> <20131028201735.GA15629@redhat.com> <20131030092725.GL4126@linux.vnet.ibm.com> <20131031043258.GQ4126@linux.vnet.ibm.com> <20131031152543.GC4067@linux.vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.6.4-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2013-11-01 at 18:30 +0200, Victor Kaplansky wrote: > "David Laight" wrote on 11/01/2013 06:25:29 PM: > > gcc will do unexpected memory accesses for bit fields that are > > adjacent to volatile data. > > In particular it may generate 64bit sized (and aligned) RMW cycles > > when accessing bit fields. > > And yes, this has caused real problems. > > Thanks, I am aware about this bug/feature in gcc. AFAIK, this has been fixed in 4.8 and 4.7.3 ... Cheers, Ben. > -- Victor > > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/linuxppc-dev From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 977322C00AD for ; Mon, 4 Nov 2013 07:58:54 +1100 (EST) Message-ID: <1383512261.4776.21.camel@pasglop> Subject: Re: perf events ring buffer memory barrier on powerpc From: Benjamin Herrenschmidt To: Victor Kaplansky Date: Mon, 04 Nov 2013 07:57:41 +1100 In-Reply-To: References: <20131028132634.GO19466@laptop.lan> <20131028163418.GD4126@linux.vnet.ibm.com> <20131028201735.GA15629@redhat.com> <20131030092725.GL4126@linux.vnet.ibm.com> <20131031043258.GQ4126@linux.vnet.ibm.com> <20131031152543.GC4067@linux.vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Cc: Michael Neuling , Mathieu Desnoyers , Peter Zijlstra , Frederic Weisbecker , LKML , Oleg Nesterov , Linux PPC dev , David Laight , Anton Blanchard , paulmck@linux.vnet.ibm.com List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Fri, 2013-11-01 at 18:30 +0200, Victor Kaplansky wrote: > "David Laight" wrote on 11/01/2013 06:25:29 PM: > > gcc will do unexpected memory accesses for bit fields that are > > adjacent to volatile data. > > In particular it may generate 64bit sized (and aligned) RMW cycles > > when accessing bit fields. > > And yes, this has caused real problems. > > Thanks, I am aware about this bug/feature in gcc. AFAIK, this has been fixed in 4.8 and 4.7.3 ... Cheers, Ben. > -- Victor > > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/linuxppc-dev