From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vandana Kannan Subject: [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR Date: Thu, 19 Dec 2013 14:01:03 +0530 Message-ID: <1387441863-21953-6-git-send-email-vandana.kannan@intel.com> References: <1387441863-21953-1-git-send-email-vandana.kannan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 09A784074 for ; Thu, 19 Dec 2013 00:23:35 -0800 (PST) In-Reply-To: <1387441863-21953-1-git-send-email-vandana.kannan@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org For Broadwell, there is one instance of Transcoder MN values per transcoder. For dynamic switching between multiple refreshr rates, M/N values may be reprogrammed on the fly. Link N programming triggers update of all data and link M & N registers and the new M/N values will be used in the next frame that is output. v2: Incorporated Chris's review comments Changed to check for gen >=8 or gen > 5 before setting M/N registers Signed-off-by: Vandana Kannan Signed-off-by: Pradeep Bhat Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_dp.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c96ed34..be06d73 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -798,11 +798,19 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) struct drm_i915_private *dev_priv = dev->dev_private; enum transcoder transcoder = crtc->config.cpu_transcoder; - I915_WRITE(PIPE_DATA_M2(transcoder), - TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); + if (INTEL_INFO(dev)->gen >= 8) { + I915_WRITE(PIPE_DATA_M1(transcoder), + TU_SIZE(m_n->tu) | m_n->gmch_m); + I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); + I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); + I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); + } else if (INTEL_INFO(dev)->gen >= 5) { + I915_WRITE(PIPE_DATA_M2(transcoder), + TU_SIZE(m_n->tu) | m_n->gmch_m); + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); + } return; } @@ -3616,8 +3624,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) mutex_lock(&intel_dp->drrs_state.mutex); - /* Haswell and below */ - if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { + if (INTEL_INFO(dev)->gen >= 8) { + switch (index) { + case DRRS_HIGH_RR: + intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n); + break; + case DRRS_LOW_RR: + intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); + break; + }; + } else if (INTEL_INFO(dev)->gen >= 5) { + /* Haswell and below */ reg = PIPECONF(intel_crtc->config.cpu_transcoder); val = I915_READ(reg); if (index > DRRS_HIGH_RR) { -- 1.7.9.5