From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38150) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9GSa-0005eO-Sl for qemu-devel@nongnu.org; Fri, 31 Jan 2014 10:56:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W9GSZ-00055w-WD for qemu-devel@nongnu.org; Fri, 31 Jan 2014 10:56:52 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:45362) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9GSZ-00055X-Q5 for qemu-devel@nongnu.org; Fri, 31 Jan 2014 10:56:51 -0500 From: Peter Maydell Date: Fri, 31 Jan 2014 15:45:33 +0000 Message-Id: <1391183143-30724-26-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1391183143-30724-1-git-send-email-peter.maydell@linaro.org> References: <1391183143-30724-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 25/35] target-arm: Implement AArch64 dummy MDSCR_EL1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rob Herring , Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson We don't support letting the guest do debug, but Linux prods the monitor debug system control register anyway, so implement a dummy RAZ/WI version. Signed-off-by: Peter Maydell --- target-arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 0dcb5b1..b0d28ca 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1681,6 +1681,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7, .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = tlbi_aa64_vaa_write }, + /* Dummy implementation of monitor debug system control register: + * we don't support debug. + */ + { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; -- 1.8.5