From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58175) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W9JrQ-0006uS-Tr for qemu-devel@nongnu.org; Fri, 31 Jan 2014 14:34:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W9JrI-0005wb-HJ for qemu-devel@nongnu.org; Fri, 31 Jan 2014 14:34:44 -0500 From: Tom Musta Date: Fri, 31 Jan 2014 13:34:06 -0600 Message-Id: <1391196846-12188-10-git-send-email-tommusta@gmail.com> In-Reply-To: <1391196846-12188-1-git-send-email-tommusta@gmail.com> References: <1391196846-12188-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [V2 PATCH 9/9] target-ppc: Add Store Quadword Conditional List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org This patch adds the Store Quadword Conditionl (stqcx.) instruction which is introduced in Power ISA 2.07. Signed-off-by: Tom Musta --- V2: Updated linux-user/main.c to use the newly added reserve_val2. linux-user/main.c | 18 +++++++++++++++++- target-ppc/translate.c | 21 +++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index cabc9e1..6330427 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1490,7 +1490,7 @@ static int do_store_exclusive(CPUPPCState *env) { target_ulong addr; target_ulong page_addr; - target_ulong val; + target_ulong val, val2; int flags; int segv = 0; @@ -1513,6 +1513,13 @@ static int do_store_exclusive(CPUPPCState *env) case 4: segv = get_user_u32(val, addr); break; #if defined(TARGET_PPC64) case 8: segv = get_user_u64(val, addr); break; + case 16: { + segv = get_user_u64(val, addr); + if (!segv) { + segv = get_user_u64(val, addr + 8); + } + break; + } #endif default: abort(); } @@ -1524,6 +1531,15 @@ static int do_store_exclusive(CPUPPCState *env) case 4: segv = put_user_u32(val, addr); break; #if defined(TARGET_PPC64) case 8: segv = put_user_u64(val, addr); break; + case 16: { + if (val2 == env->reserve_val2) { + segv = put_user_u64(val, addr); + if (!segv) { + segv = put_user_u64(val2, addr + 8); + } + } + break; + } #endif default: abort(); } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 8257dea..c883680 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3329,6 +3329,20 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA, gen_qemu_st32(ctx, cpu_gpr[reg], EA); } else if (size == 2) { gen_qemu_st16(ctx, cpu_gpr[reg], EA); +#if defined(TARGET_PPC64) + } else if (size == 16) { + TCGv gpr1, gpr2; + if (unlikely(ctx->le_mode)) { + gpr1 = cpu_gpr[reg+1]; + gpr2 = cpu_gpr[reg]; + } else { + gpr1 = cpu_gpr[reg]; + gpr2 = cpu_gpr[reg+1]; + } + gen_qemu_st64(ctx, gpr1, EA); + gen_addr_add(ctx, EA, EA, 8); + gen_qemu_st64(ctx, gpr2, EA); +#endif } else { gen_qemu_st8(ctx, cpu_gpr[reg], EA); } @@ -3341,6 +3355,11 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA, static void gen_##name(DisasContext *ctx) \ { \ TCGv t0; \ + if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \ + gen_inval_exception(ctx, \ + POWERPC_EXCP_INVAL_INVAL); \ + return; \ + } \ gen_set_access_type(ctx, ACCESS_RES); \ t0 = tcg_temp_local_new(); \ gen_addr_reg_index(ctx, t0); \ @@ -3395,6 +3414,7 @@ static void gen_lqarx(DisasContext *ctx) /* stdcx. */ STCX(stdcx_, 8); +STCX(stqcx_, 16); #endif /* defined(TARGET_PPC64) */ /* sync */ @@ -9634,6 +9654,7 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), +GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), #endif GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), -- 1.7.1