From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40625) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WAG5u-0001oF-M1 for qemu-devel@nongnu.org; Mon, 03 Feb 2014 04:45:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WAG5n-0007TI-Ew for qemu-devel@nongnu.org; Mon, 03 Feb 2014 04:45:34 -0500 Received: from mail-qa0-x234.google.com ([2607:f8b0:400d:c00::234]:64536) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WAG5n-0007TC-8w for qemu-devel@nongnu.org; Mon, 03 Feb 2014 04:45:27 -0500 Received: by mail-qa0-f52.google.com with SMTP id j15so9579449qaq.39 for ; Mon, 03 Feb 2014 01:45:26 -0800 (PST) From: "Edgar E. Iglesias" Date: Mon, 3 Feb 2014 19:44:28 +1000 Message-Id: <1391420690-23745-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, blauwirbel@gmail.com, aliguori@amazon.com, pcrost@xilinx.com, pbonzini@redhat.com, afaerber@suse.de, aurelien@aurel32.net, rth@twiddle.net From: "Edgar E. Iglesias" Hi, I'm looking at modeling systems where multiple CPUs co-exist with different views of their attached buses/devs. With this series I'm trying to take some steps towards having an address-space per CPU. It's not complete but good enough for making it possible to model (to some extent) CPU local memories for MicroBlaze systems in emulation mode (TCG). I'm updating the petalogix-ml605 here and will follow-up later with the petalogix-s3adsp. The per-cpu address space is added into the CPUState. I tried to measure performance diff with having it in the CPUState->env. For "normal" and even for IO heavy workloads on linux kernels, the diff is not measurable. I also tested with a tight guest loop that continuously does I/O accesses and there I can see a 2.5% drop in perf. I dont think the runtime type check involved when casting from env to CS will be much of a problem. I've reordered the series and moved the AS props to the end, hoping we can get through the bulk of the series with less controversy and get it commited soon. I've kept the interface with properties to set AddressSpace pointers which I think is the more flexible approach but we can explore other ideas if there are. There is lots of future work needed, for example to transform more of the cpu_* bus accessing functions. To add more usage of AddressSpace properties to pass on address spaces to DMA models. Qtest mechanisms to target specific address spaces, etc... Cheers, Edgar v3 -> v4: Rebase, Use error_abort. v2 -> v3: Move CPU address-space prop into CPUState level. v1 -> v2: Add braces in cpu_memory_rw_debug. Avoid mixing var/code declarations in tcg_commit. Move per-cpu address space into CPUState. Reorder patch series to add the AS properties last. Edgar E. Iglesias (22): exec: Make tb_invalidate_phys_addr input an AS exec: Make iotlb_to_region input an AS exec: Always initialize MemorySection address spaces exec: Make memory_region_section_get_iotlb use section AS memory: Add MemoryListener to typedefs.h cpu: Add per-cpu address space exec: On AS changes, only flush affected CPU TLBs exec: Make ldl_*_phys input an AddressSpace exec: Make ldq/ldub_*_phys input an AddressSpace exec: Make lduw_*_phys input an AddressSpace exec: Make stq_*_phys input an AddressSpace exec: Make stl_*_phys input an AddressSpace exec: Make stl_phys_notdirty input an AddressSpace exec: Make stw_*_phys input an AddressSpace exec: Make stb_phys input an AddressSpace exec: Make cpu_physical_memory_write_rom input an AS exec: Make cpu_memory_rw_debug use the CPUs AS memory: Add address_space_find_by_name() qdev: Add qdev property type for AddressSpaces cpu: Add address-space property petalogix-ml605: Create the CPU with object_new() petalogix-ml605: Make the LMB visible only to the CPU cpu-exec.c | 5 +- cpus.c | 2 + cputlb.c | 7 +- exec.c | 183 ++++++++++++---------- hw/alpha/dp264.c | 5 +- hw/alpha/typhoon.c | 2 +- hw/arm/boot.c | 5 +- hw/arm/highbank.c | 6 +- hw/core/loader.c | 3 +- hw/core/qdev-properties-system.c | 8 + hw/core/qdev-properties.c | 54 +++++++ hw/display/sm501.c | 1 + hw/display/sm501_template.h | 2 +- hw/dma/pl080.c | 9 +- hw/dma/sun4m_iommu.c | 3 +- hw/intc/apic.c | 3 +- hw/microblaze/petalogix_ml605_mmu.c | 24 ++- hw/net/vmware_utils.h | 16 +- hw/pci/msi.c | 2 +- hw/pci/msix.c | 2 +- hw/ppc/ppc405_uc.c | 45 +++--- hw/ppc/spapr_hcall.c | 50 +++--- hw/s390x/css.c | 11 +- hw/s390x/s390-virtio-bus.c | 36 +++-- hw/s390x/s390-virtio.c | 2 +- hw/s390x/virtio-ccw.c | 40 +++-- hw/scsi/megasas.c | 22 ++- hw/scsi/vmw_pvscsi.c | 6 +- hw/sh4/r2d.c | 4 +- hw/sparc/sun4m.c | 3 +- hw/timer/hpet.c | 3 +- hw/virtio/virtio.c | 31 ++-- include/exec/cpu-common.h | 44 +++--- include/exec/exec-all.h | 5 +- include/exec/memory.h | 11 +- include/exec/softmmu_template.h | 7 +- include/hw/ppc/spapr.h | 4 +- include/hw/qdev-properties.h | 5 + include/qemu/typedefs.h | 1 + include/qom/cpu.h | 3 + memory.c | 12 ++ monitor.c | 2 +- qom/cpu.c | 7 + stubs/Makefile.objs | 1 + stubs/memory.c | 6 + target-alpha/helper.c | 7 +- target-alpha/helper.h | 8 +- target-alpha/mem_helper.c | 36 +++-- target-alpha/translate.c | 8 +- target-arm/helper.c | 21 ++- target-i386/arch_memory_mapping.c | 46 +++--- target-i386/helper.c | 48 +++--- target-i386/seg_helper.c | 14 +- target-i386/smm_helper.c | 300 ++++++++++++++++++------------------ target-i386/svm_helper.c | 299 +++++++++++++++++++++-------------- target-ppc/excp_helper.c | 4 +- target-ppc/mmu-hash32.h | 12 +- target-ppc/mmu-hash64.h | 14 +- target-s390x/cpu.c | 2 +- target-s390x/helper.c | 11 +- target-s390x/mem_helper.c | 9 +- target-sparc/ldst_helper.c | 72 +++++---- target-sparc/mmu_helper.c | 22 +-- target-unicore32/softmmu.c | 5 +- target-xtensa/helper.c | 3 +- target-xtensa/op_helper.c | 3 +- translate-all.c | 14 +- 67 files changed, 990 insertions(+), 671 deletions(-) create mode 100644 stubs/memory.c -- 1.8.1.2