From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vandana Kannan Subject: [PATCH 4/5] drm/i915: Idleness detection for DRRS Date: Fri, 14 Feb 2014 15:32:21 +0530 Message-ID: <1392372142-16905-5-git-send-email-vandana.kannan@intel.com> References: <1392372142-16905-1-git-send-email-vandana.kannan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FBDEFB4A5 for ; Fri, 14 Feb 2014 01:52:18 -0800 (PST) In-Reply-To: <1392372142-16905-1-git-send-email-vandana.kannan@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Adding support to detect display idleness by tracking page flip from user space. Switch to low refresh rate is triggered after 2 seconds of idleness. The delay is configurable. If there is a page flip or call to update the plane, then high refresh rate is applied. The feature is not used in dual-display mode. v2: Chris Wilson's review comments incorporated. Modify idleness detection implementation to make it similar to the implementation of intel_update_fbc/intel_disable_fbc v3: Internal review comments incorporated Add NULL pointer check in intel_disable_drrs. Add drrs calls in i9xx_crtc_enable/disable and valleyview_crtc_enable. v4: Jani's review comments incorporated. Change in sequence in intel_update_drrs. Comment modified to remove details of update param. Modified DRRS idleness interval to a module parameter. Signed-off-by: Vandana Kannan Signed-off-by: Pradeep Bhat --- drivers/gpu/drm/i915/i915_drv.h | 6 ++ drivers/gpu/drm/i915/i915_params.c | 8 ++ drivers/gpu/drm/i915/intel_display.c | 16 ++++ drivers/gpu/drm/i915/intel_dp.c | 9 +++ drivers/gpu/drm/i915/intel_drv.h | 5 +- drivers/gpu/drm/i915/intel_pm.c | 134 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 2 + 7 files changed, 179 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3dd1d7e..8cb91d1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -777,6 +777,11 @@ struct i915_fbc { struct i915_drrs { struct intel_connector *connector; struct intel_dp *dp; + struct intel_drrs_work { + struct delayed_work work; + struct drm_crtc *crtc; + int interval; + } *drrs_work; }; struct i915_psr { @@ -1976,6 +1981,7 @@ struct i915_params { bool prefault_disable; bool reset; int invert_brightness; + int drrs_interval; }; extern struct i915_params i915 __read_mostly; diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index c743057..69f8b83 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = { .prefault_disable = 0, .reset = true, .invert_brightness = 0, + .drrs_interval = 2000, }; module_param_named(modeset, i915.modeset, int, 0400); @@ -153,3 +154,10 @@ MODULE_PARM_DESC(invert_brightness, "report PCI device ID, subsystem vendor and subsystem device ID " "to dri-devel@lists.freedesktop.org, if your machine needs it. " "It will then be included in an upcoming module version."); + +module_param_named(drrs_interval, i915.drrs_interval, int, 0600); +MODULE_PARM_DESC(drrs_interval, + "DRRS idleness detection interval (default: 2000 ms)." + "If this field is set to 0, then seamless DRRS feature " + "based on idleness detection is disabled." + "The interval is to be set in milliseconds."); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4d4a0d9..86cd603 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2410,6 +2410,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, } intel_update_fbc(dev); + intel_update_drrs(dev); intel_edp_psr_update(dev); mutex_unlock(&dev->struct_mutex); @@ -3598,6 +3599,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) mutex_lock(&dev->struct_mutex); intel_update_fbc(dev); + intel_update_drrs(dev); mutex_unlock(&dev->struct_mutex); for_each_encoder_on_crtc(dev, crtc, encoder) @@ -3639,6 +3641,7 @@ static void haswell_crtc_enable_planes(struct drm_crtc *crtc) mutex_lock(&dev->struct_mutex); intel_update_fbc(dev); + intel_update_drrs(dev); mutex_unlock(&dev->struct_mutex); } @@ -3845,6 +3848,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) mutex_lock(&dev->struct_mutex); intel_update_fbc(dev); + intel_update_drrs(dev); mutex_unlock(&dev->struct_mutex); } @@ -3892,6 +3896,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) mutex_lock(&dev->struct_mutex); intel_update_fbc(dev); + intel_update_drrs(dev); mutex_unlock(&dev->struct_mutex); } @@ -4176,6 +4181,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) intel_crtc_update_cursor(crtc, true); intel_update_fbc(dev); + intel_update_drrs(dev); for_each_encoder_on_crtc(dev, crtc, encoder) encoder->enable(encoder); @@ -4221,6 +4227,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) intel_crtc_dpms_overlay(intel_crtc, true); intel_update_fbc(dev); + intel_update_drrs(dev); for_each_encoder_on_crtc(dev, crtc, encoder) encoder->enable(encoder); @@ -4286,6 +4293,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_update_fbc(dev); + intel_update_drrs(dev); } static void i9xx_crtc_off(struct drm_crtc *crtc) @@ -8281,6 +8289,10 @@ static void intel_unpin_work_fn(struct work_struct *__work) drm_gem_object_unreference(&work->pending_flip_obj->base); drm_gem_object_unreference(&work->old_fb_obj->base); + /* disable current DRRS work scheduled and restart + * to push work by another x seconds + */ + intel_update_drrs(dev); intel_update_fbc(dev); mutex_unlock(&dev->struct_mutex); @@ -8722,6 +8734,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, goto cleanup_pending; intel_disable_fbc(dev); + intel_disable_drrs(dev); intel_mark_fb_busy(obj, NULL); mutex_unlock(&dev->struct_mutex); @@ -11055,6 +11068,7 @@ void intel_modeset_init(struct drm_device *dev) /* Just in case the BIOS is doing something questionable. */ intel_disable_fbc(dev); + intel_disable_drrs(dev); } static void @@ -11461,6 +11475,8 @@ void intel_modeset_cleanup(struct drm_device *dev) intel_disable_fbc(dev); + intel_disable_drrs(dev); + intel_disable_gt_powersave(dev); ironlake_teardown_rc6(dev); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1933675..3407af6 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3411,11 +3411,17 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder) struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = &intel_dig_port->dp; struct drm_device *dev = intel_dp_to_dev(intel_dp); + struct drm_i915_private *dev_priv = dev->dev_private; i2c_del_adapter(&intel_dp->adapter); drm_encoder_cleanup(encoder); if (is_edp(intel_dp)) { cancel_delayed_work_sync(&intel_dp->panel_vdd_work); + /* DRRS cleanup */ + if (intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { + kfree(dev_priv->drrs.drrs_work); + dev_priv->drrs.drrs_work = NULL; + } mutex_lock(&dev->mode_config.mutex); edp_panel_vdd_off_sync(intel_dp); mutex_unlock(&dev->mode_config.mutex); @@ -3799,6 +3805,9 @@ intel_dp_drrs_initialize(struct intel_digital_port *intel_dig_port, dev_priv->drrs.connector = intel_connector; dev_priv->drrs.dp = intel_dp; + intel_init_drrs_idleness_detection(dev, + intel_connector, intel_dp); + mutex_init(&intel_dp->drrs_state.mutex); intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 4f7c816..c8d6aa2 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -911,7 +911,10 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv); void intel_init_runtime_pm(struct drm_i915_private *dev_priv); void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); void ilk_wm_get_hw_state(struct drm_device *dev); - +void intel_init_drrs_idleness_detection(struct drm_device *dev, + struct intel_connector *connector, struct intel_dp *dp); +void intel_update_drrs(struct drm_device *dev); +void intel_disable_drrs(struct drm_device *dev); /* intel_sdvo.c */ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9ab3883..2b84864 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -618,6 +618,140 @@ out_disable: i915_gem_stolen_cleanup_compression(dev); } +static void intel_drrs_work_fn(struct work_struct *__work) +{ + struct intel_drrs_work *work = + container_of(to_delayed_work(__work), + struct intel_drrs_work, work); + struct drm_device *dev = work->crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + intel_dp_set_drrs_state(work->crtc->dev, + dev_priv->drrs.connector->panel.downclock_mode->vrefresh); +} + +static void intel_cancel_drrs_work(struct drm_i915_private *dev_priv) +{ + if (dev_priv->drrs.drrs_work == NULL) + return; + + DRM_DEBUG_KMS("cancelling pending DRRS enable\n"); + + cancel_delayed_work_sync(&dev_priv->drrs.drrs_work->work); +} + +static void intel_enable_drrs(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + intel_cancel_drrs_work(dev_priv); + + if (dev_priv->drrs.dp->drrs_state.refresh_rate_type + != DRRS_LOW_RR) { + dev_priv->drrs.drrs_work->crtc = crtc; + + /* Delay the actual enabling to let pageflipping cease and the + * display to settle before starting DRRS + */ + schedule_delayed_work(&dev_priv->drrs.drrs_work->work, + msecs_to_jiffies(dev_priv->drrs.drrs_work->interval)); + } +} + +void intel_disable_drrs(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (dev_priv->drrs.dp == NULL) { + DRM_DEBUG_KMS("DRRS is not supported.\n"); + return; + } + + /* as part of disable DRRS, reset refresh rate to HIGH_RR */ + if (dev_priv->drrs.dp->drrs_state.refresh_rate_type + == DRRS_LOW_RR) { + intel_cancel_drrs_work(dev_priv); + intel_dp_set_drrs_state(dev, + dev_priv->drrs.connector->panel.fixed_mode->vrefresh); + } +} + +/** + * intel_update_drrs - enable/disable DRRS as needed + * @dev: the drm_device +*/ +void intel_update_drrs(struct drm_device *dev) +{ + struct drm_crtc *crtc = NULL, *tmp_crtc; + struct drm_i915_private *dev_priv = dev->dev_private; + + /* if drrs.connector is NULL, then drrs_init did not get called. + * which means DRRS is not supported. + */ + if (dev_priv->drrs.connector == NULL) { + DRM_DEBUG_KMS("DRRS is not supported.\n"); + return; + } + + if (dev_priv->drrs.connector->panel.downclock_mode == NULL) { + DRM_DEBUG_KMS( + "No downclock mode found. DRRS not supported\n"); + return; + } + + list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { + if (tmp_crtc != NULL && intel_crtc_active(tmp_crtc) && + to_intel_crtc(tmp_crtc)->primary_enabled) { + if (crtc) { + DRM_DEBUG_KMS( + "more than one pipe active, disabling DRRS\n"); + intel_disable_drrs(dev); + return; + } + crtc = tmp_crtc; + } + } + + if (crtc == NULL) { + DRM_DEBUG_KMS("DRRS: crtc not initialized\n"); + return; + } + + intel_disable_drrs(dev); + + /* re-enable idleness detection */ + intel_enable_drrs(crtc); +} + +void intel_init_drrs_idleness_detection(struct drm_device *dev, + struct intel_connector *connector, + struct intel_dp *dp) +{ + struct intel_drrs_work *work; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (i915.drrs_interval == 0) { + DRM_INFO("DRRS disable by flag\n"); + dev_priv->drrs.connector = NULL; + dev_priv->drrs.dp = NULL; + return; + } + + work = kzalloc(sizeof(struct intel_drrs_work), GFP_KERNEL); + if (!work) { + DRM_ERROR("Failed to allocate DRRS work structure\n"); + dev_priv->drrs.connector = NULL; + dev_priv->drrs.dp = NULL; + return; + } + + work->interval = i915.drrs_interval; + INIT_DELAYED_WORK(&work->work, intel_drrs_work_fn); + + dev_priv->drrs.drrs_work = work; +} + static void i915_pineview_get_mem_freq(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 336ae6c..6c465cd 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -547,6 +547,7 @@ intel_enable_primary(struct drm_crtc *crtc) mutex_lock(&dev->struct_mutex); intel_update_fbc(dev); + intel_update_drrs(dev); mutex_unlock(&dev->struct_mutex); } @@ -566,6 +567,7 @@ intel_disable_primary(struct drm_crtc *crtc) mutex_lock(&dev->struct_mutex); if (dev_priv->fbc.plane == intel_crtc->plane) intel_disable_fbc(dev); + intel_disable_drrs(dev); mutex_unlock(&dev->struct_mutex); /* -- 1.7.9.5