From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752365AbaBNLYQ (ORCPT ); Fri, 14 Feb 2014 06:24:16 -0500 Received: from mail-wg0-f47.google.com ([74.125.82.47]:51587 "EHLO mail-wg0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752177AbaBNLYP (ORCPT ); Fri, 14 Feb 2014 06:24:15 -0500 From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: alexandre.torgue@st.com, Lee Jones , devicetree@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 3/4] ARM: DT: STi: Add DT node for MiPHY365x Date: Fri, 14 Feb 2014 11:23:55 +0000 Message-Id: <1392377036-12816-3-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1392377036-12816-1-git-send-email-lee.jones@linaro.org> References: <1392377036-12816-1-git-send-email-lee.jones@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Cc: devicetree@vger.kernel.org Cc: Srinivas Kandagatla Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih416-b2020-revE.dts | 6 +++++- arch/arm/boot/dts/stih416-b2020.dts | 6 ++++++ arch/arm/boot/dts/stih416.dtsi | 13 +++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts b/arch/arm/boot/dts/stih416-b2020-revE.dts index a874570..dbe67fa 100644 --- a/arch/arm/boot/dts/stih416-b2020-revE.dts +++ b/arch/arm/boot/dts/stih416-b2020-revE.dts @@ -32,6 +32,10 @@ ethernet1: ethernet@fef08000 { snps,reset-gpio = <&PIO0 7>; }; - }; + miphy365x_phy: miphy365x@0 { + st,pcie_tx_pol_inv = <1>; + st,sata_gen = "gen3"; + }; + }; }; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts index 276f28d..fd9cbad 100644 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ b/arch/arm/boot/dts/stih416-b2020.dts @@ -13,4 +13,10 @@ model = "STiH416 B2020"; compatible = "st,stih416", "st,stih416-b2020"; + soc { + miphy365x_phy: miphy365x@0 { + st,pcie_tx_pol_inv = <1>; + st,sata_gen = "gen3"; + }; + }; }; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 85b8063..9fd8efb 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,8 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" + +#include #include #include / { @@ -140,5 +142,16 @@ clocks = <&CLK_S_ICN_REG_0>; }; + miphy365x_phy: miphy365x@0 { + compatible = "st,miphy365x-phy"; + reg = <0xfe382000 0x100>, + <0xfe38a000 0x100>, + <0xfe394000 0x100>, + <0xfe804000 0x100>; + reg-names = "sata0", "sata1", "pcie0", "pcie1"; + + #phy-cells = <2>; + st,syscfg = <&syscfg_rear>; + }; }; }; -- 1.8.3.2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: lee.jones@linaro.org (Lee Jones) Date: Fri, 14 Feb 2014 11:23:55 +0000 Subject: [PATCH 3/4] ARM: DT: STi: Add DT node for MiPHY365x In-Reply-To: <1392377036-12816-1-git-send-email-lee.jones@linaro.org> References: <1392377036-12816-1-git-send-email-lee.jones@linaro.org> Message-ID: <1392377036-12816-3-git-send-email-lee.jones@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Cc: devicetree at vger.kernel.org Cc: Srinivas Kandagatla Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih416-b2020-revE.dts | 6 +++++- arch/arm/boot/dts/stih416-b2020.dts | 6 ++++++ arch/arm/boot/dts/stih416.dtsi | 13 +++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts b/arch/arm/boot/dts/stih416-b2020-revE.dts index a874570..dbe67fa 100644 --- a/arch/arm/boot/dts/stih416-b2020-revE.dts +++ b/arch/arm/boot/dts/stih416-b2020-revE.dts @@ -32,6 +32,10 @@ ethernet1: ethernet at fef08000 { snps,reset-gpio = <&PIO0 7>; }; - }; + miphy365x_phy: miphy365x at 0 { + st,pcie_tx_pol_inv = <1>; + st,sata_gen = "gen3"; + }; + }; }; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts index 276f28d..fd9cbad 100644 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ b/arch/arm/boot/dts/stih416-b2020.dts @@ -13,4 +13,10 @@ model = "STiH416 B2020"; compatible = "st,stih416", "st,stih416-b2020"; + soc { + miphy365x_phy: miphy365x at 0 { + st,pcie_tx_pol_inv = <1>; + st,sata_gen = "gen3"; + }; + }; }; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 85b8063..9fd8efb 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,8 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" + +#include #include #include / { @@ -140,5 +142,16 @@ clocks = <&CLK_S_ICN_REG_0>; }; + miphy365x_phy: miphy365x at 0 { + compatible = "st,miphy365x-phy"; + reg = <0xfe382000 0x100>, + <0xfe38a000 0x100>, + <0xfe394000 0x100>, + <0xfe804000 0x100>; + reg-names = "sata0", "sata1", "pcie0", "pcie1"; + + #phy-cells = <2>; + st,syscfg = <&syscfg_rear>; + }; }; }; -- 1.8.3.2