From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60365) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFZIP-0005IE-3T for qemu-devel@nongnu.org; Mon, 17 Feb 2014 20:16:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WFZIJ-0007aC-Ms for qemu-devel@nongnu.org; Mon, 17 Feb 2014 20:16:24 -0500 Received: from mail-qa0-x230.google.com ([2607:f8b0:400d:c00::230]:58578) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFZIJ-0007a7-Ib for qemu-devel@nongnu.org; Mon, 17 Feb 2014 20:16:19 -0500 Received: by mail-qa0-f48.google.com with SMTP id f11so22763155qae.35 for ; Mon, 17 Feb 2014 17:16:19 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Mon, 17 Feb 2014 19:15:56 -0600 Message-Id: <1392686165-10706-7-git-send-email-rth@twiddle.net> In-Reply-To: <1392686165-10706-1-git-send-email-rth@twiddle.net> References: <1392686165-10706-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 06/15] tcg/optimize: add known-zero bits compute for load ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno From: Aurelien Jarno Reviewed-by: Paolo Bonzini Signed-off-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/optimize.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 1cf017a..1b9fea5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -779,13 +779,37 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, mask = temps[args[3]].mask | temps[args[4]].mask; break; + CASE_OP_32_64(ld8u): + case INDEX_op_qemu_ld8u: + mask = 0xff; + break; + CASE_OP_32_64(ld16u): + case INDEX_op_qemu_ld16u: + mask = 0xffff; + break; + case INDEX_op_ld32u_i64: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_qemu_ld32u: +#endif + mask = 0xffffffffu; + break; + + CASE_OP_32_64(qemu_ld): + { + TCGMemOp mop = args[def->nb_oargs + def->nb_iargs]; + if (!(mop & MO_SIGN)) { + mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; + } + } + break; + default: break; } /* 32-bit ops (non 64-bit ops and non load/store ops) generate 32-bit results */ - if (!(tcg_op_defs[op].flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT))) { + if (!(def->flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT))) { mask &= 0xffffffffu; } -- 1.8.5.3