From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WILHX-0003Lv-KG for qemu-devel@nongnu.org; Tue, 25 Feb 2014 11:55:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WILHR-0002S0-GW for qemu-devel@nongnu.org; Tue, 25 Feb 2014 11:54:59 -0500 Received: from mail-we0-f180.google.com ([74.125.82.180]:52199) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WILHR-0002Rv-A8 for qemu-devel@nongnu.org; Tue, 25 Feb 2014 11:54:53 -0500 Received: by mail-we0-f180.google.com with SMTP id u57so637444wes.39 for ; Tue, 25 Feb 2014 08:54:52 -0800 (PST) From: Alvise Rigo Date: Tue, 25 Feb 2014 17:52:49 +0100 Message-Id: <1393347170-28502-4-git-send-email-a.rigo@virtualopensystems.com> In-Reply-To: <1393347170-28502-1-git-send-email-a.rigo@virtualopensystems.com> References: <1393347170-28502-1-git-send-email-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [RFC 3/4] Add l2ctlr cp register to CPUARMState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , tech@virtualopensystems.com, Alvise Rigo Since the irq bit seems to not be updated, exclude it from the check done while copying data during migration. Signed-off-by: Alvise Rigo --- target-arm/cpu.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 6e7ce89..e8db00e 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -681,20 +681,34 @@ static void cortex_a9_initfn(Object *obj) } #ifndef CONFIG_USER_ONLY -static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +static void a15_l2ctlr_reset(CPUARMState *env, const ARMCPRegInfo *opaque) { /* Linux wants the number of processors from here. * Might as well set the interrupt-controller bit too. */ - return ((smp_cpus - 1) << 24) | (1 << 23); + env->cp15.c9_l2ctlr = ((smp_cpus - 1) << 24) | (1 << 23); +} + +static void a15_l2ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int smp_cpus_new = ((value >> 24) & 3); + int smp_cpus_old = ((env->cp15.c9_l2ctlr >> 24) & 3); + + if (smp_cpus_new != smp_cpus_old) { + return; + } + + env->cp15.c9_l2ctlr = value; } #endif static const ARMCPRegInfo cortexa15_cp_reginfo[] = { #ifndef CONFIG_USER_ONLY { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, - .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, - .writefn = arm_cp_write_ignore, }, + .access = PL1_RW, .resetvalue = 0, + .resetfn = a15_l2ctlr_reset, .writefn = a15_l2ctlr_write, + .fieldoffset = offsetof(CPUARMState, cp15.c9_l2ctlr) }, #endif { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, -- 1.8.3.2