[U-Boot] [PATCH v3] socfpga: Adding Clock Manager driver

* [U-Boot] [PATCH v3] socfpga: Adding Clock Manager driver
@ 2014-03-05  4:13 Chin Liang See
  2014-03-05 16:08 ` Pavel Machek
  2014-04-07  9:06 ` Albert ARIBAUD
  0 siblings, 2 replies; 3+ messages in thread
From: Chin Liang See @ 2014-03-05  4:13 UTC (permalink / raw)
  To: u-boot

Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
---
Changes for v3
- Shorten some variables name
- Fixed some coding style
Changes for v2
- merge the handoff file and driver into single patch
---
 arch/arm/cpu/armv7/socfpga/Makefile                |    2 +-
 arch/arm/cpu/armv7/socfpga/clock_manager.c         |  361 ++++++++++++++++++++
 arch/arm/cpu/armv7/socfpga/spl.c                   |   89 +++++
 arch/arm/include/asm/arch-socfpga/clock_manager.h  |  205 +++++++++++
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |    1 +
 board/altera/socfpga/pll_config.h                  |  118 +++++++
 include/configs/socfpga_cyclone5.h                 |    1 +
 7 files changed, 776 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/socfpga/clock_manager.c
 create mode 100644 arch/arm/include/asm/arch-socfpga/clock_manager.h
 create mode 100644 board/altera/socfpga/pll_config.h

diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..cbe1d40 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -8,5 +8,5 @@
 #
 
 obj-y	:= lowlevel_init.o
-obj-y	+= misc.o timer.o reset_manager.o system_manager.o
+obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
new file mode 100644
index 0000000..23d697d
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -0,0 +1,361 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+
+static const struct socfpga_clock_manager *clock_manager_base =
+		(void *)SOCFPGA_CLKMGR_ADDRESS;
+
+#define CLKMGR_BYPASS_ENABLE	1
+#define CLKMGR_BYPASS_DISABLE	0
+#define CLKMGR_STAT_IDLE	0
+#define CLKMGR_STAT_BUSY	1
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1		0
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX	1
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1		0
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX	1
+
+#define CLEAR_BGP_EN_PWRDN \
+	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+#define VCO_EN_BASE \
+	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
+	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+static inline void cm_wait_for_lock(uint32_t mask)
+{
+	register uint32_t inter_val;
+	do {
+		inter_val = readl(&clock_manager_base->inter) & mask;
+	} while (inter_val != mask);
+}
+
+/* function to poll in the fsm busy bit */
+static inline void cm_wait_for_fsm(void)
+{
+	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
+		;
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static inline void cm_write_bypass(uint32_t val)
+{
+	writel(val, &clock_manager_base->bypass);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static inline void cm_write_ctrl(uint32_t val)
+{
+	writel(val, &clock_manager_base->ctrl);
+	cm_wait_for_fsm();
+}
+
+/* function to write a clock register that has phase information */
+static inline void cm_write_with_phase(uint32_t value,
+	uint32_t reg_address, uint32_t mask)
+{
+	/* poll until phase is zero */
+	while (readl(reg_address) & mask)
+		;
+
+	writel(value, reg_address);
+
+	while (readl(reg_address) & mask)
+		;
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ * Put all plls in bypass
+ * Put all plls VCO registers back to reset value (bandgap power down).
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ * Delay 5 us.
+ * Deassert bandgap power down and set numerator and denominator
+ * Start 7 us timer.
+ * set internal dividers
+ * Wait for 7 us timer.
+ * Enable plls
+ * Set external dividers while plls are locking
+ * Wait for pll lock
+ * Assert/deassert outreset all.
+ * Take all pll's out of bypass
+ * Clear safe mode
+ * set source main and peripheral clocks
+ * Ungate clocks
+ */
+
+void cm_basic_init(const cm_config_t *cfg)
+{
+	uint32_t start, timeout;
+
+	/* Start by being paranoid and gate all sw managed clocks */
+
+	/*
+	 * We need to disable nandclk
+	 * and then do another apb access before disabling
+	 * gatting off the rest of the periperal clocks.
+	 */
+	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
+		readl(&clock_manager_base->per_pll_en),
+		&clock_manager_base->per_pll_en);
+
+	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
+	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
+		&clock_manager_base->main_pll_en);
+
+	writel(0, &clock_manager_base->sdr_pll_en);
+
+	/* now we can gate off the rest of the peripheral clocks */
+	writel(0, &clock_manager_base->per_pll_en);
+
+	/* Put all plls in bypass */
+	cm_write_bypass(
+		CLKMGR_BYPASS_PERPLLSRC_SET(
+		CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_SDRPLLSRC_SET(
+		CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
+		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
+		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+
+	/*
+	 * Put all plls VCO registers back to reset value.
+	 * Some code might have messed with them.
+	 */
+	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->main_pll_vco);
+	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->per_pll_vco);
+	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * The clocks to the flash devices and the L4_MAIN clocks can
+	 * glitch when coming out of safe mode if their source values
+	 * are different from their reset value.  So the trick it to
+	 * put them back to their reset state, and change input
+	 * after exiting safe mode but before ungating the clocks.
+	 */
+	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
+	       &clock_manager_base->per_pll_src);
+	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
+	       &clock_manager_base->main_pll_l4src);
+
+	/* read back for the required 5 us delay. */
+	readl(&clock_manager_base->main_pll_vco);
+	readl(&clock_manager_base->per_pll_vco);
+	readl(&clock_manager_base->sdr_pll_vco);
+
+
+	/*
+	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
+	 * with numerator and denominator.
+	 */
+	writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->main_pll_vco);
+
+	writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->per_pll_vco);
+
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * Time starts here
+	 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
+	 */
+	reset_timer();
+	start = get_timer(0);
+	/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
+	timeout = 7;
+
+	/* main mpu */
+	writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
+
+	/* main main clock */
+	writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
+
+	/* main for dbg */
+	writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
+
+	/* main for cfgs2fuser0clk */
+	writel(cfg->cfg2fuser0clk,
+	       &clock_manager_base->main_pll_cfgs2fuser0clk);
+
+	/* Peri emac0 50 MHz default to RMII */
+	writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
+
+	/* Peri emac1 50 MHz default to RMII */
+	writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
+
+	/* Peri QSPI */
+	writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
+
+	writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
+
+	/* Peri pernandsdmmcclk */
+	writel(cfg->pernandsdmmcclk,
+	       &clock_manager_base->per_pll_pernandsdmmcclk);
+
+	/* Peri perbaseclk */
+	writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
+
+	/* Peri s2fuser1clk */
+	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
+
+	/* 7 us must have elapsed before we can enable the VCO */
+	while (get_timer(start) < timeout)
+		;
+
+	/* Enable vco */
+	/* main pll vco */
+	writel(cfg->main_vco_base | VCO_EN_BASE,
+	       &clock_manager_base->main_pll_vco);
+
+	/* periferal pll */
+	writel(cfg->peri_vco_base | VCO_EN_BASE,
+	       &clock_manager_base->per_pll_vco);
+
+	/* sdram pll vco */
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | VCO_EN_BASE,
+		&clock_manager_base->sdr_pll_vco);
+
+	/* L3 MP and L3 SP */
+	writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
+
+	writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
+
+	writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
+
+	/* L4 MP, L4 SP, can0, and can1 */
+	writel(cfg->perdiv, &clock_manager_base->per_pll_div);
+
+	writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
+
+#define LOCKED_MASK \
+	(CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
+	CLKMGR_INTER_PERPLLLOCKED_MASK  | \
+	CLKMGR_INTER_MAINPLLLOCKED_MASK)
+
+	cm_wait_for_lock(LOCKED_MASK);
+
+	/* write the sdram clock counters before toggling outreset all */
+	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddrdqsclk);
+
+	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddr2xdqsclk);
+
+	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddrdqclk);
+
+	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_s2fuser2clk);
+
+	/*
+	 * after locking, but before taking out of bypass
+	 * assert/deassert outresetall
+	 */
+	uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
+
+	/* assert main outresetall */
+	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll_vco);
+
+	uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
+
+	/* assert pheriph outresetall */
+	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll_vco);
+
+	/* assert sdram outresetall */
+	writel(cfg->sdram_vco_base | VCO_EN_BASE|
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+		&clock_manager_base->sdr_pll_vco);
+
+	/* deassert main outresetall */
+	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll_vco);
+
+	/* deassert pheriph outresetall */
+	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll_vco);
+
+	/* deassert sdram outresetall */
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | VCO_EN_BASE,
+		&clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * now that we've toggled outreset all, all the clocks
+	 * are aligned nicely; so we can change any phase.
+	 */
+	cm_write_with_phase(cfg->ddrdqsclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
+			    CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
+
+	/* SDRAM DDR2XDQSCLK */
+	cm_write_with_phase(cfg->ddr2xdqsclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
+			    CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
+
+	cm_write_with_phase(cfg->ddrdqclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
+			    CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
+
+	cm_write_with_phase(cfg->s2fuser2clk,
+			    (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
+			    CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
+
+	/* Take all three PLLs out of bypass when safe mode is cleared. */
+	cm_write_bypass(
+		CLKMGR_BYPASS_PERPLLSRC_SET(
+			CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_SDRPLLSRC_SET(
+			CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
+		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
+		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
+
+	/* clear safe mode */
+	cm_write_ctrl(readl(&clock_manager_base->ctrl) |
+			CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
+
+	/*
+	 * now that safe mode is clear with clocks gated
+	 * it safe to change the source mux for the flashes the the L4_MAIN
+	 */
+	writel(cfg->persrc, &clock_manager_base->per_pll_src);
+	writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
+
+	/* Now ungate non-hw-managed clocks */
+	writel(~0, &clock_manager_base->main_pll_en);
+	writel(~0, &clock_manager_base->per_pll_en);
+	writel(~0, &clock_manager_base->sdr_pll_en);
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 36a00c3..2ae88bb 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -28,10 +28,99 @@ u32 spl_boot_device(void)
 void spl_board_init(void)
 {
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+	cm_config_t cm_default_cfg = {
+		/* main group */
+		MAIN_VCO_BASE,
+		CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
+		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
+		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
+		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
+			CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
+		CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
+			CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
+		CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
+			CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
+
+		/* peripheral group */
+		PERI_VCO_BASE,
+		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
+		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
+		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
+		CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
+		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
+		CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
+		CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
+		CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
+		CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
+		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
+			CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
+		CLKMGR_PERPLLGRP_SRC_QSPI_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
+		CLKMGR_PERPLLGRP_SRC_NAND_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_NAND) |
+		CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
+
+		/* sdram pll group */
+		SDR_VCO_BASE,
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
+		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
+	};
+
 	debug("Freezing all I/O banks\n");
 	/* freeze all IO banks */
 	sys_mgr_frzctrl_freeze_req();
 
+	debug("Reconfigure Clock Manager\n");
+	/* reconfigure the PLLs */
+	cm_basic_init(&cm_default_cfg);
+
 	/* configure the pin muxing through system manager */
 	sysmgr_pinmux_init();
 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h
new file mode 100644
index 0000000..966add3
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h
@@ -0,0 +1,205 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_CLOCK_MANAGER_H_
+#define	_CLOCK_MANAGER_H_
+
+typedef struct {
+	/* main group */
+	uint32_t main_vco_base;
+	uint32_t mpuclk;
+	uint32_t mainclk;
+	uint32_t dbgatclk;
+	uint32_t mainqspiclk;
+	uint32_t mainnandsdmmcclk;
+	uint32_t cfg2fuser0clk;
+	uint32_t maindiv;
+	uint32_t dbgdiv;
+	uint32_t tracediv;
+	uint32_t l4src;
+
+	/* peripheral group */
+	uint32_t peri_vco_base;
+	uint32_t emac0clk;
+	uint32_t emac1clk;
+	uint32_t perqspiclk;
+	uint32_t pernandsdmmcclk;
+	uint32_t perbaseclk;
+	uint32_t s2fuser1clk;
+	uint32_t perdiv;
+	uint32_t gpiodiv;
+	uint32_t persrc;
+
+	/* sdram pll group */
+	uint32_t sdram_vco_base;
+	uint32_t ddrdqsclk;
+	uint32_t ddr2xdqsclk;
+	uint32_t ddrdqclk;
+	uint32_t s2fuser2clk;
+} cm_config_t;
+
+extern void cm_basic_init(const cm_config_t *cfg);
+
+struct socfpga_clock_manager {
+	u32	ctrl;
+	u32	bypass;
+	u32	inter;
+	u32	intren;
+	u32	dbctrl;
+	u32	stat;
+	u32	_pad_0x18_0x3f[10];
+	u32	mainpllgrp;
+	u32	perpllgrp;
+	u32	sdrpllgrp;
+	u32	_pad_0xe0_0x200[72];
+
+	u32	main_pll_vco;
+	u32	main_pll_misc;
+	u32	main_pll_mpuclk;
+	u32	main_pll_mainclk;
+	u32	main_pll_dbgatclk;
+	u32	main_pll_mainqspiclk;
+	u32	main_pll_mainnandsdmmcclk;
+	u32	main_pll_cfgs2fuser0clk;
+	u32	main_pll_en;
+	u32	main_pll_maindiv;
+	u32	main_pll_dbgdiv;
+	u32	main_pll_tracediv;
+	u32	main_pll_l4src;
+	u32	main_pll_stat;
+	u32	main_pll__pad_0x38_0x40[2];
+
+	u32	per_pll_vco;
+	u32	per_pll_misc;
+	u32	per_pll_emac0clk;
+	u32	per_pll_emac1clk;
+	u32	per_pll_perqspiclk;
+	u32	per_pll_pernandsdmmcclk;
+	u32	per_pll_perbaseclk;
+	u32	per_pll_s2fuser1clk;
+	u32	per_pll_en;
+	u32	per_pll_div;
+	u32	per_pll_gpiodiv;
+	u32	per_pll_src;
+	u32	per_pll_stat;
+	u32	per_pll__pad_0x34_0x40[3];
+
+	u32	sdr_pll_vco;
+	u32	sdr_pll_ctrl;
+	u32	sdr_pll_ddrdqsclk;
+	u32	sdr_pll_ddr2xdqsclk;
+	u32	sdr_pll_ddrdqclk;
+	u32	sdr_pll_s2fuser2clk;
+	u32	sdr_pll_en;
+	u32	sdr_pll_stat;
+};
+
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x)  (((x) << 7) & 0x00000380)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
+#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
+	(((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
+	(((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
+#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
+#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
+#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
+#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
+#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
+
+#define MAIN_VCO_BASE \
+	(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
+	CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
+
+#define PERI_VCO_BASE \
+	(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
+	CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
+	CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
+
+#define SDR_VCO_BASE \
+	(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
+	CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
+	CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
+
+#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index 50c4ebd..f564046 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -11,6 +11,7 @@
 #define SOCFPGA_UART0_ADDRESS 0xffc02000
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
 
diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h
new file mode 100644
index 0000000..9bd0442
--- /dev/null
+++ b/board/altera/socfpga/pll_config.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ */
+
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+/* PLL configuration data */
+/* Main PLL */
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM			(0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER			(63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT		(0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT		(0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT		(0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		(3)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT	(3)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT	(12)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK		(0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK		(0)
+/*
+ * To tell where is the clock source:
+ * 0 = MAINPLL
+ * 1 = PERIPHPLL
+ */
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP		(1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP		(1)
+
+/* Peripheral PLL */
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM			(1)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER			(79)
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC			(0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT		(3)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT		(3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT		(1)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT	(4)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT		(4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT		(9)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK			(0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK		(0)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK		(1)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK		(1)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK		(6249)
+/*
+ * To tell where is the clock source:
+ * 0 = F2S_PERIPH_REF_CLK
+ * 1 = MAIN_CLK
+ * 2 = PERIPH_CLK
+ */
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC			(2)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND			(2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI			(1)
+
+/* SDRAM PLL */
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* Arria V SDRAM will run at 533MHz while Cyclone V still@400MHz
+ * This if..else... is not required if generated by tools */
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM			(2)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(127)
+#else
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM			(0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(31)
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC			(0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT		(1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE		(0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT		(0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE		(0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT		(1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE		(4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT		(5)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE		(0)
+
+/* Info for driver */
+#define CONFIG_HPS_CLK_OSC1_HZ			(25000000)
+#define CONFIG_HPS_CLK_MAINVCO_HZ		(1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ		(1000000000)
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define CONFIG_HPS_CLK_SDRVCO_HZ		(1066000000)
+#else
+#define CONFIG_HPS_CLK_SDRVCO_HZ		(800000000)
+#endif
+#define CONFIG_HPS_CLK_EMAC0_HZ			(250000000)
+#define CONFIG_HPS_CLK_EMAC1_HZ			(250000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ		(200000000)
+#define CONFIG_HPS_CLK_NAND_HZ			(50000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ			(200000000)
+#define CONFIG_HPS_CLK_QSPI_HZ			(400000000)
+#define CONFIG_HPS_CLK_SPIM_HZ			(200000000)
+#define CONFIG_HPS_CLK_CAN0_HZ			(100000000)
+#define CONFIG_HPS_CLK_CAN1_HZ			(100000000)
+#define CONFIG_HPS_CLK_GPIODB_HZ		(32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ			(100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ			(100000000)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 608578a..0254249 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -8,6 +8,7 @@
 
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
 
 /*
  * High level configuration
-- 
1.7.9.5

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