From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37564) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLePY-0002ru-1q for qemu-devel@nongnu.org; Thu, 06 Mar 2014 14:56:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WLePW-0002Rq-Pl for qemu-devel@nongnu.org; Thu, 06 Mar 2014 14:56:56 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46390) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLePW-0002Qz-JZ for qemu-devel@nongnu.org; Thu, 06 Mar 2014 14:56:54 -0500 From: Peter Maydell Date: Thu, 6 Mar 2014 19:32:55 +0000 Message-Id: <1394134385-1727-12-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1394134385-1727-1-git-send-email-peter.maydell@linaro.org> References: <1394134385-1727-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v4 11/21] target-arm: Don't mention PMU in debug feature register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rob Herring , Peter Crosthwaite , patches@linaro.org, Michael Matz , Claudio Fontana , Alexander Graf , Will Newton , Dirk Mueller , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Suppress the ID_AA64DFR0_EL1 PMUVer field, even if the CPU specific value claims that it exists. QEMU doesn't currently implement it, and not advertising it prevents the guest from trying to use it and getting UNDEFs on unimplemented registers. Signed-off-by: Peter Maydell --- This is arguably a hack, but otherwise Linux tries to prod half a dozen PMU sysregs. --- target-arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index c18f1a6..e1672aa 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1929,7 +1929,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = cpu->id_aa64dfr0 }, + /* We mask out the PMUVer field, beacuse we don't currently + * implement the PMU. Not advertising it prevents the guest + * from trying to use it and getting UNDEFs on registers we + * don't implement. + */ + .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, -- 1.9.0