From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 5/6] drm/i915: BDW needs D_COMP writes through MCHBAR
Date: Fri, 7 Mar 2014 20:12:36 -0300 [thread overview]
Message-ID: <1394233957-3904-6-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1394233957-3904-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
That's what the spec said! And HSW needs it through pcode (you can
only read it through MCHBAR), so create hsw_write_dcomp to abstract
the weirdness.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d6092be..2be4129 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6664,6 +6664,22 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
+static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
+{
+ struct drm_device *dev = dev_priv->dev;
+
+ if (IS_HASWELL(dev)) {
+ mutex_lock(&dev_priv->rps.hw_lock);
+ if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
+ val))
+ DRM_ERROR("Failed to disable D_COMP\n");
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ } else {
+ I915_WRITE(D_COMP, val);
+ }
+ POSTING_READ(D_COMP);
+}
+
/*
* This function implements pieces of two sequences from BSpec:
* - Sequence for display software to disable LCPLL
@@ -6701,11 +6717,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
val = I915_READ(D_COMP);
val |= D_COMP_COMP_DISABLE;
- mutex_lock(&dev_priv->rps.hw_lock);
- if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
- DRM_ERROR("Failed to disable D_COMP\n");
- mutex_unlock(&dev_priv->rps.hw_lock);
- POSTING_READ(D_COMP);
+ hsw_write_dcomp(dev_priv, val);
ndelay(100);
if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
@@ -6760,11 +6772,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
val = I915_READ(D_COMP);
val |= D_COMP_COMP_FORCE;
val &= ~D_COMP_COMP_DISABLE;
- mutex_lock(&dev_priv->rps.hw_lock);
- if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
- DRM_ERROR("Failed to enable D_COMP\n");
- mutex_unlock(&dev_priv->rps.hw_lock);
- POSTING_READ(D_COMP);
+ hsw_write_dcomp(dev_priv, val);
val = I915_READ(LCPLL_CTL);
val &= ~LCPLL_PLL_DISABLE;
--
1.8.5.3
next prev parent reply other threads:[~2014-03-07 23:12 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-07 23:12 [PATCH 0/6] SNB/BDW runtime PM Paulo Zanoni
2014-03-07 23:12 ` [PATCH 1/6] drm/i915: kill dev_priv->pm.regsave Paulo Zanoni
2014-03-20 12:58 ` Imre Deak
2014-04-01 20:54 ` Paulo Zanoni
2014-03-07 23:12 ` [PATCH 2/6] drm/i915: add gen-specific runtime suspend/resume functions Paulo Zanoni
2014-03-20 12:59 ` Imre Deak
2014-03-07 23:12 ` [PATCH 3/6] drm/i915: add SNB runtime PM support Paulo Zanoni
2014-04-01 15:34 ` Imre Deak
2014-04-01 21:17 ` Paulo Zanoni
2014-03-07 23:12 ` [PATCH 4/6] drm/i915: remove HAS_PC8 check Paulo Zanoni
2014-03-20 13:29 ` Imre Deak
2014-03-07 23:12 ` Paulo Zanoni [this message]
2014-04-01 15:49 ` [PATCH 5/6] drm/i915: BDW needs D_COMP writes through MCHBAR Imre Deak
2014-03-07 23:12 ` [PATCH 6/6] drm/i915: add BDW runtime PM support Paulo Zanoni
2014-04-01 15:51 ` Imre Deak
2014-04-01 21:35 ` Daniel Vetter
2014-04-01 16:21 ` [PATCH 0/6] SNB/BDW runtime PM Imre Deak
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