From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39787) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPcQO-0005xx-Vi for qemu-devel@nongnu.org; Mon, 17 Mar 2014 14:38:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPcQG-0001NA-B2 for qemu-devel@nongnu.org; Mon, 17 Mar 2014 14:38:12 -0400 Received: from mail-qg0-x22b.google.com ([2607:f8b0:400d:c04::22b]:42746) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPcQG-0001N6-5x for qemu-devel@nongnu.org; Mon, 17 Mar 2014 14:38:04 -0400 Received: by mail-qg0-f43.google.com with SMTP id f51so17811338qge.2 for ; Mon, 17 Mar 2014 11:38:03 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 17 Mar 2014 11:37:42 -0700 Message-Id: <1395081476-6038-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 00/14] tcg/sparc v8plus code generation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, aurelien@aurel32.net Our 32-bit build for sparc has been requiring a 64-bit capable chip for about 2 years now, by way of requiring move-conditional and LE memory instructions. But we've mostly been generating 32-bit code otherwise. This patch set changes things so that we make full use of the cpu. The sparcv8plus code model requires that 64-bit data be kept only in the %g and %o registers. These are saved by the kernel in full 64-bit slots somewhere. Whereas the %i and %l registers are saved via the register window mechanism, and as part of the 32-bit ABI we've only allocated 32-bits of stack for storing these. Since the register window can roll at any time, due to signals and interrupts, we must consider the high bits of %i and %l to be garbage. This implies that we must treat 32-bit and 64-bit quantities differently. For the most part, TCG is good with that. The one case where that falls down, however, is when we frob data between widths. Thus the addition of the trunc_i32 opcode. This new opcode, or something like it, would have been required if we ever got around to supporting MIPS64 code generation, where 32-bit quantities must remain sign-extended in the 64-bit register at all times. In the case of sparcv8plus, we can get what we need out of the opcode merely by setting its register constraints properly. r~ Richard Henderson (14): tcg: Fix missed pointer size != TCG_TARGET_REG_BITS changes tcg: Add INDEX_op_trunc_i32 tcg-sparc: Remove most uses of TCG_TARGET_REG_BITS tcg-sparc: Support trunc_i32 tcg-sparc: Use 64-bit registers with sparcv8plus tcg-sparc: Use the RETURN instruction tcg-sparc: Implement muls2_i32 tcg-sparc: Tidy check_fit_* tests tcg-sparc: Don't handle mov/movi in tcg_out_op tcg-sparc: Hoist common argument loads in tcg_out_op tcg-sparc: Fixup function argument types tcg-sparc: Fix small 32-bit movi tcg-sparc: Fix 32-bit constant arguments tests tcg-sparc: Accept stores of zero include/exec/def-helper.h | 2 +- tcg/README | 5 + tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ia64/tcg-target.h | 1 + tcg/optimize.c | 16 + tcg/ppc64/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.c | 903 ++++++++++++++++++++-------------------------- tcg/sparc/tcg-target.h | 21 +- tcg/tcg-op.h | 54 ++- tcg/tcg-opc.h | 4 + tcg/tcg.c | 45 ++- tcg/tcg.h | 1 + tcg/tci/tcg-target.h | 1 + 15 files changed, 503 insertions(+), 554 deletions(-) -- 1.8.5.3