From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39816) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPcQR-0005y4-0W for qemu-devel@nongnu.org; Mon, 17 Mar 2014 14:38:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPcQL-0001c4-4A for qemu-devel@nongnu.org; Mon, 17 Mar 2014 14:38:14 -0400 Received: from mail-qg0-x22e.google.com ([2607:f8b0:400d:c04::22e]:39366) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPcQK-0001ap-VL for qemu-devel@nongnu.org; Mon, 17 Mar 2014 14:38:09 -0400 Received: by mail-qg0-f46.google.com with SMTP id e89so17806875qgf.5 for ; Mon, 17 Mar 2014 11:38:08 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 17 Mar 2014 11:37:44 -0700 Message-Id: <1395081476-6038-3-git-send-email-rth@twiddle.net> In-Reply-To: <1395081476-6038-1-git-send-email-rth@twiddle.net> References: <1395081476-6038-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 02/14] tcg: Add INDEX_op_trunc_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, aurelien@aurel32.net Let the backend do something special for truncation. Signed-off-by: Richard Henderson --- tcg/README | 5 +++++ tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ia64/tcg-target.h | 1 + tcg/optimize.c | 16 ++++++++++++++++ tcg/ppc64/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tcg-op.h | 50 ++++++++++++++++++++++++++++++++---------------- tcg/tcg-opc.h | 4 ++++ tcg/tcg.h | 1 + tcg/tci/tcg-target.h | 1 + 12 files changed, 67 insertions(+), 16 deletions(-) diff --git a/tcg/README b/tcg/README index f178212..160cbe8 100644 --- a/tcg/README +++ b/tcg/README @@ -306,6 +306,11 @@ This operation would be equivalent to dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00) +* trunc_i32 t0, t1, pos + +For 64-bit hosts only, right shift the 64-bit input T1 by POS and +truncate to 32-bit output T0. Depending on the host, this may be +a simple mov/shift, or may require additional canonicalization. ********* Conditional moves diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 988983e..6363151 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -63,6 +63,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_trunc_i32 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index bdf2222..de34269 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -101,6 +101,7 @@ extern bool have_bmi1; #define TCG_TARGET_HAS_mulsh_i32 0 #if TCG_TARGET_REG_BITS == 64 +#define TCG_TARGET_HAS_trunc_i32 0 #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h index 52a939c..4962dca 100644 --- a/tcg/ia64/tcg-target.h +++ b/tcg/ia64/tcg-target.h @@ -152,6 +152,7 @@ typedef enum { #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_trunc_i32 0 #define TCG_TARGET_HAS_new_ldst 0 diff --git a/tcg/optimize.c b/tcg/optimize.c index 7777743..fee3292 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -228,6 +228,7 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) case INDEX_op_shr_i32: return (uint32_t)x >> (uint32_t)y; + case INDEX_op_trunc_i32: case INDEX_op_shr_i64: return (uint64_t)x >> (uint64_t)y; @@ -826,6 +827,10 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, } break; + case INDEX_op_trunc_i32: + mask = (uint64_t)temps[args[1]].mask >> args[2]; + break; + CASE_OP_32_64(shl): if (temps[args[2]].state == TCG_TEMP_CONST) { mask = temps[args[1]].mask << temps[args[2]].val; @@ -1017,6 +1022,17 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, } goto do_default; + case INDEX_op_trunc_i32: + if (temps[args[1]].state == TCG_TEMP_CONST) { + s->gen_opc_buf[op_index] = op_to_movi(op); + tmp = do_constant_folding(op, temps[args[1]].val, args[2]); + tcg_opt_gen_movi(gen_args, args[0], tmp); + gen_args += 2; + args += 3; + break; + } + goto do_default; + CASE_OP_32_64(add): CASE_OP_32_64(sub): CASE_OP_32_64(mul): diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 7ee50b6..52a8127 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -97,6 +97,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_trunc_i32 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 0 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 10adb77..192cdbb 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -71,6 +71,7 @@ typedef enum TCGReg { #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_trunc_i32 0 #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 3abf1b4..8c3a8a4 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -119,6 +119,7 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i32 0 #if TCG_TARGET_REG_BITS == 64 +#define TCG_TARGET_HAS_trunc_i32 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 0 #define TCG_TARGET_HAS_rot_i64 0 diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 4089d89..71820b1 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1624,9 +1624,20 @@ static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } -static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) +static inline void tcg_gen_trunc_rshift_i64_i32(TCGv_i32 ret, TCGv_i64 arg, + unsigned int count) { - tcg_gen_mov_i32(ret, TCGV_LOW(arg)); + tcg_debug_assert(count < 64); + if (count >= 32) { + tcg_gen_shri_i32(ret, TCGV_HIGH(arg), count - 32); + } else if (count == 0) { + tcg_gen_mov_i32(ret, TCGV_LOW(arg)); + } else { + TCGv_i64 t = tcg_temp_new_i64(); + tcg_gen_shri_i64(t, arg, count); + tcg_gen_mov_i32(ret, TCGV_LOW(t)); + tcg_temp_free_i64(t); + } } static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) @@ -1727,11 +1738,21 @@ static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) } } -/* Note: we assume the target supports move between 32 and 64 bit - registers. This will probably break MIPS64 targets. */ -static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) +static inline void tcg_gen_trunc_rshift_i64_i32(TCGv_i32 ret, TCGv_i64 arg, + unsigned int count) { - tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); + tcg_debug_assert(count < 64); + if (TCG_TARGET_HAS_trunc_i32) { + tcg_gen_op3i_i32(INDEX_op_trunc_i32, ret, + MAKE_TCGV_I32(GET_TCGV_I64(arg)), count); + } else if (count == 0) { + tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); + } else { + TCGv_i64 t = tcg_temp_new_i64(); + tcg_gen_shri_i64(t, arg, count); + tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(t))); + tcg_temp_free_i64(t); + } } /* Note: we assume the target supports move between 32 and 64 bit @@ -2275,18 +2296,15 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, tcg_gen_deposit_i64(dest, low, high, 32, 32); } +static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) +{ + tcg_gen_trunc_rshift_i64_i32(ret, arg, 0); +} + static inline void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg) { -#if TCG_TARGET_REG_BITS == 32 - tcg_gen_mov_i32(lo, TCGV_LOW(arg)); - tcg_gen_mov_i32(hi, TCGV_HIGH(arg)); -#else - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_trunc_i64_i32(lo, arg); - tcg_gen_shri_i64(t0, arg, 32); - tcg_gen_trunc_i64_i32(hi, t0); - tcg_temp_free_i64(t0); -#endif + tcg_gen_trunc_rshift_i64_i32(lo, arg, 0); + tcg_gen_trunc_rshift_i64_i32(hi, arg, 32); } static inline void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index d71707d..ae06e27 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -147,6 +147,10 @@ DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64)) +DEF(trunc_i32, 1, 1, 1, + IMPL(TCG_TARGET_HAS_trunc_i32) + | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) + DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64) DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64)) DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64)) diff --git a/tcg/tcg.h b/tcg/tcg.h index f7efcb4..c336227 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -66,6 +66,7 @@ typedef uint64_t TCGRegSet; #if TCG_TARGET_REG_BITS == 32 /* Turn some undef macros into false macros. */ +#define TCG_TARGET_HAS_trunc_i32 0 #define TCG_TARGET_HAS_div_i64 0 #define TCG_TARGET_HAS_rem_i64 0 #define TCG_TARGET_HAS_div2_i64 0 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 6e1da8c..fdd5ada 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -88,6 +88,7 @@ #define TCG_TARGET_HAS_mulsh_i32 0 #if TCG_TARGET_REG_BITS == 64 +#define TCG_TARGET_HAS_trunc_i32 0 #define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 -- 1.8.5.3