From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: [PATCH 00/12] [v3] BDW RPS + RC6 + rps fixlets Date: Wed, 19 Mar 2014 18:31:07 -0700 Message-ID: <1395279079-12704-1-git-send-email-benjamin.widawsky@intel.com> References: <1392692512-2268-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 2C85E890BE for ; Wed, 19 Mar 2014 18:31:29 -0700 (PDT) In-Reply-To: <1392692512-2268-1-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Intel GFX List-Id: intel-gfx@lists.freedesktop.org Ben Widawsky (12): drm/i915: Reorganize the overclock code drm/i915: Fix coding style for RPS drm/i915: Store the HW min frequency as min_freq drm/i915: Rename and comment all the RPS *stuff* drm/i915: Remove extraneous MMIO for RPS drm/i915: remove rps local variables drm/i915/bdw: Set initial rps freq to RP0 drm/i915/bdw: Extract rp_state_caps logic drm/i915/bdw: RPS frequency bits are the same as HSW drm/i915/bdw: Implement a basic PM interrupt handler drm/i915/bdw: Ensure a context is loaded before RC6 drm/i915/bdw: Enable RC6 drivers/gpu/drm/i915/i915_debugfs.c | 26 ++--- drivers/gpu/drm/i915/i915_drv.c | 4 +- drivers/gpu/drm/i915/i915_drv.h | 25 ++-- drivers/gpu/drm/i915/i915_gem.c | 10 ++ drivers/gpu/drm/i915/i915_irq.c | 109 +++++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/i915_sysfs.c | 81 ++++++------- drivers/gpu/drm/i915/intel_display.c | 5 + drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 213 +++++++++++++++++++++-------------- 10 files changed, 306 insertions(+), 170 deletions(-) -- 1.9.0