From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTa-00005P-G0 for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WQkTV-0003vM-Mx for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:10 -0400 Received: from mail-ee0-x22d.google.com ([2a00:1450:4013:c00::22d]:32770) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTV-0003vE-GX for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:05 -0400 Received: by mail-ee0-f45.google.com with SMTP id d17so1146347eek.4 for ; Thu, 20 Mar 2014 14:26:04 -0700 (PDT) From: Beniamino Galvani Date: Thu, 20 Mar 2014 22:25:15 +0100 Message-Id: <1395350719-3778-4-git-send-email-b.galvani@gmail.com> In-Reply-To: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> References: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH v4 3/7] allwinner-a10-pit: avoid generation of spurious interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang The model was generating interrupts for all enabled timers after the expiration of one of them. Avoid this by passing explicitly the timer index to the callback function. Signed-off-by: Beniamino Galvani Reviewed-by: Li Guang Reviewed-by: Peter Crosthwaite --- hw/timer/allwinner-a10-pit.c | 25 ++++++++++++++----------- include/hw/timer/allwinner-a10-pit.h | 8 ++++++++ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index b27fce8..696b7d9 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -193,18 +193,17 @@ static void a10_pit_reset(DeviceState *dev) static void a10_pit_timer_cb(void *opaque) { - AwA10PITState *s = AW_A10_PIT(opaque); - uint8_t i; + AwA10TimerContext *tc = opaque; + AwA10PITState *s = tc->container; + uint8_t i = tc->index; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - if (s->control[i] & AW_A10_PIT_TIMER_EN) { - s->irq_status |= 1 << i; - if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->timer[i]); - s->control[i] &= ~AW_A10_PIT_TIMER_EN; - } - qemu_irq_pulse(s->irq[i]); + if (s->control[i] & AW_A10_PIT_TIMER_EN) { + s->irq_status |= 1 << i; + if (s->control[i] & AW_A10_PIT_TIMER_MODE) { + ptimer_stop(s->timer[i]); + s->control[i] &= ~AW_A10_PIT_TIMER_EN; } + qemu_irq_pulse(s->irq[i]); } } @@ -223,7 +222,11 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - bh[i] = qemu_bh_new(a10_pit_timer_cb, s); + AwA10TimerContext *tc = &s->timer_context[i]; + + tc->container = s; + tc->index = i; + bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); s->timer[i] = ptimer_init(bh[i]); ptimer_set_freq(s->timer[i], 240000); } diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 15efab8..a48d3c7 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -35,12 +35,20 @@ #define AW_A10_PIT_DEFAULT_CLOCK 0x4 +typedef struct AwA10PITState AwA10PITState; + +typedef struct AwA10TimerContext { + AwA10PITState *container; + int index; +} AwA10TimerContext; + typedef struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ qemu_irq irq[AW_A10_PIT_TIMER_NR]; ptimer_state * timer[AW_A10_PIT_TIMER_NR]; + AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; MemoryRegion iomem; uint32_t irq_enable; -- 1.7.10.4