From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Gupta, Sourab" Subject: Re: [PATCH v2 1/3] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' Date: Fri, 21 Mar 2014 11:50:20 +0000 Message-ID: <1395402656.19358.27.camel@sourabgu-desktop> References: <1391775732-7431-1-git-send-email-akash.goel@intel.com> <1391775732-7431-2-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 21BBB6E2D8 for ; Fri, 21 Mar 2014 04:50:26 -0700 (PDT) In-Reply-To: <1391775732-7431-2-git-send-email-akash.goel@intel.com> Content-Language: en-US Content-ID: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "ville.syrjala@linux.intel.com" Cc: "intel-gfx@lists.freedesktop.org" , "Goel, Akash" List-Id: intel-gfx@lists.freedesktop.org On Fri, 2014-02-07 at 12:22 +0000, Goel, Akash wrote: > From: Akash Goel > > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'. > In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI > Store data commands. > > v2: Modified the WA comment. (Ville) > > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index d897a19..2ac6600 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -2183,6 +2183,29 @@ intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) > uint32_t flush_domains; > int ret; > > + if (IS_VALLEYVIEW(ring->dev)) { > + /* > + * WaTlbInvalidateStoreDataBefore > + * Before pipecontrol with TLB invalidate set, need 2 store > + * data commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) > + * Without this, hardware cannot guarantee the command after the > + * PIPE_CONTROL with TLB inv will not use the old TLB values. > + * FIXME, should also apply to snb, ivb > + */ > + int i; > + ret = intel_ring_begin(ring, 4 * 2); > + if (ret) > + return ret; > + for (i = 0; i < 2; i++) { > + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); > + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << > + MI_STORE_DWORD_INDEX_SHIFT); > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, MI_NOOP); > + } > + intel_ring_advance(ring); > + } > + > flush_domains = 0; > if (ring->gpu_caches_dirty) > flush_domains = I915_GEM_GPU_DOMAINS; > -- > 1.8.5.2 > Hi Ville, Can you please let us know the status of this patch, as there are no further comments to address here. Regards, Sourab