From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kuo-Jung Su Date: Wed, 26 Mar 2014 14:03:14 +0800 Subject: [U-Boot] [PATCH v11 1/6] arm: add Faraday ARMv5TE cores support In-Reply-To: <1395813799-3672-1-git-send-email-dantesu@gmail.com> References: <1395813799-3672-1-git-send-email-dantesu@gmail.com> Message-ID: <1395813799-3672-2-git-send-email-dantesu@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Kuo-Jung Su Here is the list of verified cores: 1. FA606TE (ARMv5TE, no mmu) 2. FA626TE (ARMv5TE) Signed-off-by: Kuo-Jung Su CC: Albert Aribaud --- Changes for v11: - Nothing updates Changes for v10: - Merge [arm: add Faraday SoC helper files] Changes for v9: - Build 'arch_preboot_os()' only when CONFIG_CMD_BOOTM is defined. - Add do_go_exec() to override the default behavior of 'go' command. Changes for v8: - add arm_init_before_mmu() & mmu_page_table_flush() Changes for v7: - Update license to use SPDX identifiers. Changes for v6: - Nothing updates Changes for v5: - Initial commit arch/arm/cpu/faraday/Makefile | 10 + arch/arm/cpu/faraday/cache.c | 164 +++++++++++++++ arch/arm/cpu/faraday/config.mk | 15 ++ arch/arm/cpu/faraday/cpu.c | 115 +++++++++++ arch/arm/cpu/faraday/start.S | 407 ++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/faraday.h | 13 ++ include/common.h | 3 + include/configs/faraday-common.h | 314 +++++++++++++++++++++++++++++ 8 files changed, 1041 insertions(+) create mode 100644 arch/arm/cpu/faraday/Makefile create mode 100644 arch/arm/cpu/faraday/cache.c create mode 100644 arch/arm/cpu/faraday/config.mk create mode 100644 arch/arm/cpu/faraday/cpu.c create mode 100644 arch/arm/cpu/faraday/start.S create mode 100644 arch/arm/include/asm/faraday.h create mode 100644 include/configs/faraday-common.h diff --git a/arch/arm/cpu/faraday/Makefile b/arch/arm/cpu/faraday/Makefile new file mode 100644 index 0000000..c859238 --- /dev/null +++ b/arch/arm/cpu/faraday/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y := start.o + +obj-y += cpu.o cache.o diff --git a/arch/arm/cpu/faraday/cache.c b/arch/arm/cpu/faraday/cache.c new file mode 100644 index 0000000..2acb954 --- /dev/null +++ b/arch/arm/cpu/faraday/cache.c @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2013 + * Faraday Technology Corporation. + * Kuo-Jung Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + * I-Cache + */ + +void invalidate_icache_all(void) +{ +#if !defined(CONFIG_SYS_ICACHE_OFF) + asm volatile ( + "mov r0, #0\n" + "mcr p15, 0, r0, c7, c5, 0\n" + : /* output */ + : /* input */ + : "r0" + ); +#endif /* !CONFIG_SYS_ICACHE_OFF */ +} + +/* + * D-Cache + */ + +void flush_dcache_all(void) +{ +#if !defined(CONFIG_SYS_DCACHE_OFF) + asm volatile ( + "mov r0, #0\n" + "mcr p15, 0, r0, c7, c14, 0\n" /* clean & invalidate */ + "mcr p15, 0, r0, c7, c10, 4\n" /* drain write buffer */ + : /* output */ + : /* input */ + : "r0" + ); +#endif /* !CONFIG_SYS_DCACHE_OFF */ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +#if !defined(CONFIG_SYS_DCACHE_OFF) + unsigned long line = CONFIG_SYS_CACHELINE_SIZE; + unsigned long mask = ~(line - 1); + + /* aligned to cache line */ + stop = (line - 1 + stop) & mask; + start = start & mask; + + asm volatile ( + "1:\n" + "mcr p15, 0, %0, c7, c14, 1\n" /* clean & invalidate */ + "add %0, %0, %2\n" + "cmp %0, %1\n" + "blo 1b\n" + "mov r0, #0\n" + "mcr p15, 0, r0, c7, c10, 4\n" /* drain write buffer */ + : "+r"(start) + : "r"(stop), "r"(line) + : "r0" + ); +#endif /* !CONFIG_SYS_DCACHE_OFF */ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +#if !defined(CONFIG_SYS_DCACHE_OFF) + unsigned long line = CONFIG_SYS_CACHELINE_SIZE; + unsigned long mask = ~(line - 1); + + /* aligned to cache line */ + stop = (line - 1 + stop) & mask; + start = start & mask; + + asm volatile ( + "1:\n" + "mcr p15, 0, %0, c7, c6, 1\n" + "add %0, %0, %2\n" + "cmp %0, %1\n" + "blo 1b\n" + : "+r"(start) + : "r"(stop), "r"(line) + ); +#endif /* !CONFIG_SYS_DCACHE_OFF */ +} + +void invalidate_dcache_all(void) +{ +#if !defined(CONFIG_SYS_DCACHE_OFF) + asm volatile ( + "mov r0, #0\n" + "mcr p15, 0, r0, c7, c6, 0\n" + : /* output */ + : /* input */ + : "r0" + ); +#endif /* !CONFIG_SYS_DCACHE_OFF */ +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} + +/* + * MMU + */ + +static void invalidate_utlb_all(void) +{ +#if !defined(CONFIG_SYS_DCACHE_OFF) + asm volatile ( + "mov r0, #0\n" + "mcr p15, 0, r0, c8, c7, 0\n" + : /* output */ + : /* input */ + : "r0" + ); +#endif /* !CONFIG_SYS_DCACHE_OFF */ +} + +static void invalidate_utlb_range(unsigned long start, unsigned long stop) +{ +#if !defined(CONFIG_SYS_DCACHE_OFF) + uint32_t page = 4096; + uint32_t mask = ~(page - 1); + + /* aligned to page boundary */ + stop = (page - 1 + stop) & mask; + start = start & mask; + + /* invalidate U-TLB entry */ + asm volatile ( + "1:\n" + "mcr p15, 0, %0, c8, c7, 1\n" + "add %0, %0, %1\n" + "cmp %0, %2\n" + "blo 1b\n" + : "+r"(start) + : "r"(page), "r"(stop) + ); +#endif /* !CONFIG_SYS_DCACHE_OFF */ +} + +void arm_init_before_mmu(void) +{ + invalidate_dcache_all(); + invalidate_utlb_all(); +} + +void mmu_page_table_flush(unsigned long start, unsigned long stop) +{ + flush_dcache_range(start, stop); + invalidate_utlb_range(start, stop); +} diff --git a/arch/arm/cpu/faraday/config.mk b/arch/arm/cpu/faraday/config.mk new file mode 100644 index 0000000..f39e70b --- /dev/null +++ b/arch/arm/cpu/faraday/config.mk @@ -0,0 +1,15 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -march=armv5te +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/faraday/cpu.c b/arch/arm/cpu/faraday/cpu.c new file mode 100644 index 0000000..8eef357 --- /dev/null +++ b/arch/arm/cpu/faraday/cpu.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2013 + * Faraday Technology Corporation. + * Kuo-Jung Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * This enable_caches() overrides the weak function + * in "arch/arm/lib/cache.c". + */ +void enable_caches(void) +{ + icache_enable(); + dcache_enable(); +} + +int cleanup_before_linux(void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + disable_interrupts(); + + /* + * Turn off I-cache and invalidate it + */ + icache_disable(); + invalidate_icache_all(); + + /* + * Turn off D-cache + * dcache_disable() in turn flushes the d-cache and disables MMU + */ + dcache_disable(); + + /* + * After D-cache is flushed and before it is disabled there may + * be some new valid entries brought into the cache. We are sure + * that these lines are not dirty and will not affect our execution. + * So just invalidate the entire d-cache again to avoid coherency + * problems for kernel + */ + invalidate_dcache_all(); + + return 0; +} + +void reset_cpu(unsigned long ignored) +{ +#ifdef CONFIG_FTWDT010_BASE + struct ftwdt010_wdt *regs = (void __iomem *)CONFIG_FTWDT010_BASE; + + /* Disable WDT */ + writel(0, ®s->wdcr); + /* Timeout in 1000 ticks */ + writel(1000, ®s->wdload); + /* Enable WDT with system reset */ + writel(FTWDT010_WDCR_ENABLE | FTWDT010_WDCR_RST, ®s->wdcr); +#endif +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + /* print cpu_info */ + printf("CPU: %u MHz\n", + (unsigned int)(clk_get_rate("CPU") / 1000000)); + + printf("AHB: %u MHz\n", + (unsigned int)(clk_get_rate("AHB") / 1000000)); + + printf("APB: %u MHz\n", + (unsigned int)(clk_get_rate("APB") / 1000000)); + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_CMD_GO +/* + * This do_go_exec() overrides the weak function + * in "cmd_boot.c". + */ +unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, + char * const argv[]) +{ + cleanup_before_linux(); + return entry(argc, argv); +} +#endif /* CONFIG_CMD_GO */ + +#ifdef CONFIG_CMD_BOOTM +/* + * This arch_preboot_os() overrides the weak function + * in "cmd_bootm.c". + */ +void arch_preboot_os(void) +{ + cleanup_before_linux(); +} +#endif /* CONFIG_CMD_BOOTM */ diff --git a/arch/arm/cpu/faraday/start.S b/arch/arm/cpu/faraday/start.S new file mode 100644 index 0000000..32ce92e --- /dev/null +++ b/arch/arm/cpu/faraday/start.S @@ -0,0 +1,407 @@ +/* + * u-boot - Startup Code for Faraday CPU-core + * + * Base is arch/arm/cpu/arm926ejs/start.S + * + * (C) Copyright 2013 Faraday Technology + * Kuo-Jung Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG +.globl _start +_start: +.globl _NOR_BOOT_CFG +_NOR_BOOT_CFG: + .word CONFIG_SYS_DV_NOR_BOOT_CFG + b reset +#else +.globl _start +_start: + b reset +#endif +#ifdef CONFIG_SPL_BUILD +/* No exception handlers in preloader */ + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang +/* pad to 64 byte boundary */ + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 +#else + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: + .word undefined_instruction +_software_interrupt: + .word software_interrupt +_prefetch_abort: + .word prefetch_abort +_data_abort: + .word data_abort +_not_used: + .word not_used +_irq: + .word irq +_fiq: + .word fiq + +#endif /* CONFIG_SPL_BUILD */ + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +.globl _TEXT_BASE +_TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else + .word CONFIG_SYS_TEXT_BASE +#endif + +/* + * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. + */ +.globl _bss_start_ofs +_bss_start_ofs: + .word __bss_start - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .word __bss_end - _start + +.globl _end_ofs +_end_ofs: + .word _end - _start + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + /* + * With the following bootstrap relocation, we could flawless + * boot from either ROM or NOR flash. + */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + teq r0, r1 /* don't reloc during debug */ + bleq _main + ldr r2, _end_ofs /* r2 <- size of u-boot */ + add r2, r0, r2 /* r2 <- source end address */ + +reloc_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + blo reloc_loop + + ldr pc, =_main + +/*----------------------------------------------------------------------*/ + + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + mov pc, lr + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + /* + * flush D cache before disabling it + */ + mov r0, #0 + mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ + mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + + /* + * disable MMU and D cache + * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ +#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH + orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ +#else + bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ +#endif + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ +#ifndef CONFIG_SYS_ICACHE_OFF + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ +#endif + mcr p15, 0, r0, c1, c0, 0 + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + mov ip, lr /* perserve link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#ifndef CONFIG_SPL_BUILD +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + @ carve out a frame on current user stack + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + ldr r2, IRQ_STACK_START_IN + @ get values for "aborted" pc and cpsr (into parm regs) + ldmia r2, {r2 - r3} + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm +#endif /* CONFIG_SPL_BUILD */ + +/* + * exception handlers + */ +#ifdef CONFIG_SPL_BUILD + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* switch to abort stack */ +1: + bl 1b /* hang and never return */ +#else /* !CONFIG_SPL_BUILD */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/include/asm/faraday.h b/arch/arm/include/asm/faraday.h new file mode 100644 index 0000000..2b59af1 --- /dev/null +++ b/arch/arm/include/asm/faraday.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 Faraday Technology + * Dante Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_FARADAY_H +#define _ASM_FARADAY_H + +ulong clk_get_rate(const char *id); + +#endif /* EOF */ diff --git a/include/common.h b/include/common.h index 5c9bd08..de3120c 100644 --- a/include/common.h +++ b/include/common.h @@ -88,6 +88,9 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_SOC_DA8XX #include #endif +#ifdef CONFIG_SOC_FARADAY +#include +#endif #include #include diff --git a/include/configs/faraday-common.h b/include/configs/faraday-common.h new file mode 100644 index 0000000..546c0a9 --- /dev/null +++ b/include/configs/faraday-common.h @@ -0,0 +1,314 @@ +/* + * (C) Copyright 2013 + * Faraday Technology Corporation. + * Kuo-Jung Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_FARADAY_COMMON_H +#define __CONFIG_FARADAY_COMMON_H + +/* Faraday SoC Platform */ +#define CONFIG_SOC_FARADAY +#define CONFIG_MACH_TYPE 758 /* Faraday */ + +/* Faraday ARMv5TE cores are 32 bytes per line */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#ifdef CONFIG_SPL_BUILD +# undef CONFIG_USE_IRQ +# ifndef CONFIG_SYS_DCACHE_OFF +# define CONFIG_SYS_DCACHE_OFF +# endif +# ifndef CONFIG_SYS_THUMB_BUILD +# define CONFIG_SYS_THUMB_BUILD +# endif +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_DISPLAY_CPUINFO + +#ifndef CONFIG_SYS_DCACHE_OFF +# define CONFIG_SYS_ARM_CACHE_WRITETHROUGH +#endif + +#ifdef CONFIG_USE_IRQ +# define CONFIG_STACKSIZE_IRQ SZ_32K +# define CONFIG_STACKSIZE_FIQ SZ_32K +#endif + +#define CONFIG_SYS_HZ 1000 + +/* + * Initial stack pointer: GENERATED_GBL_DATA_SIZE in internal SRAM. + * Inside the board_init_f, the gd is first assigned to + * (CONFIG_SYS_INIT_SP_ADDR) & ~0x07) and then relocated to DRAM + * while calling relocate_code. + */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN SZ_512K + +#ifndef CONFIG_CONSISTENT_DMA_START +#define CONFIG_CONSISTENT_DMA_START 0xff000000 +#endif + +#ifndef CONFIG_CONSISTENT_DMA_END +#define CONFIG_CONSISTENT_DMA_END 0xfff00000 +#endif + +/* Default entry point */ +#ifndef CONFIG_SYS_UBOOT_START +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#endif + +/* Default load address */ +#ifndef CONFIG_SYS_LOAD_ADDR +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_8M) +#endif + +/* U-Boot's built-in memory test */ +#ifndef CONFIG_SYS_MEMTEST_START +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_8M) +#endif + +#ifndef CONFIG_SYS_MEMTEST_END +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + SZ_32M) +#endif + +/* + * Serial driver + */ +#ifdef CONFIG_FTUART010 +# ifndef CONFIG_FTUART010_CLK +# define CONFIG_FTUART010_CLK 18432000 +# endif +# ifndef CONFIG_BAUDRATE +# define CONFIG_BAUDRATE 38400 +# endif +# undef CONFIG_HWFLOW +# undef CONFIG_MODEM_SUPPORT +# define CONFIG_SYS_NS16550 +# define CONFIG_SYS_NS16550_SERIAL +# define CONFIG_SYS_NS16550_CLK CONFIG_FTUART010_CLK +# define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_BASE +# define CONFIG_SYS_NS16550_MEM32 +# define CONFIG_SYS_NS16550_REG_SIZE (-4) +# define CONFIG_CONS_INDEX 1 +#endif /* CONFIG_FTUART010 */ + +/* + * NIC driver + */ +#ifdef CONFIG_FTGMAC100 +# define CONFIG_FTGMAC100_EGIGA +# define CONFIG_PHY_GIGE /* Enable giga phy support for miiphyutil.c */ +#endif + +#if defined(CONFIG_FTMAC110) || defined(CONFIG_FTGMAC100) +# define CONFIG_PHY_MAX_ADDR 32 +# define CONFIG_RANDOM_MACADDR +# define CONFIG_MII +# define CONFIG_NET_MULTI +# define CONFIG_NET_RETRY_COUNT 20 +# define CONFIG_DRIVER_ETHER +# define CONFIG_CMD_MII +# define CONFIG_CMD_PING +#endif /* CONFIG_FTMAC110 || CONFIG_FTGMAC100 */ + +#ifndef CONFIG_ETHADDR +#define CONFIG_ETHADDR 00:41:71:00:00:50 +#endif + +#ifndef CONFIG_IPADDR +#define CONFIG_IPADDR 10.0.0.192 +#endif + +#ifndef CONFIG_NETMASK +#define CONFIG_NETMASK 255.255.255.0 +#endif + +#ifndef CONFIG_SERVERIP +#define CONFIG_SERVERIP 10.0.0.128 +#endif + +/* + * I2C bus driver + */ +#ifdef CONFIG_FTI2C010 +# define CONFIG_SYS_I2C_FTI2C010 +#endif +#ifdef CONFIG_SYS_I2C_FTI2C010 +# define CONFIG_SYS_I2C +# define CONFIG_SYS_I2C_SPEED 5000 +# define CONFIG_SYS_I2C_SLAVE 0 +# define CONFIG_CMD_I2C +# define CONFIG_I2C_CMD_TREE +#endif /* CONFIG_FTI2C010 */ + +/* + * I2C-EEPROM + */ +#ifdef CONFIG_ENV_EEPROM_IS_ON_I2C +# define CONFIG_CMD_EEPROM +# define CONFIG_SYS_I2C_MULTI_EEPROMS +# ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS +# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +# endif +# ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS +# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +# endif +# ifndef CONFIG_SYS_I2C_EEPROM_ADDR_LEN +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +# endif +#endif + +/* + * NAND flash controller + */ +#ifdef CONFIG_FTNANDC021 +# define CONFIG_NAND_FTNANDC021 +#endif +#ifdef CONFIG_SYS_NAND_BASE +# define CONFIG_MTD_NAND_VERIFY_WRITE +# define CONFIG_CMD_NAND +# define CONFIG_CMD_NAND_YAFFS +#endif + +/* + * NOR flash driver + */ +#ifdef CONFIG_SYS_FLASH_BASE +# define CONFIG_SYS_FLASH_CFI +# define CONFIG_FLASH_CFI_DRIVER +# define CFG_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ +# define CONFIG_CMD_IMLS +# define CONFIG_CMD_FLASH +#else +# define CONFIG_SYS_NO_FLASH +#endif /* !CONFIG_SYS_NO_FLASH */ + +/* + * MMC/SD + */ +#ifdef CONFIG_FTSDC010 +# define CONFIG_FTSDC010_SDIO /* HW is configured with SDIO support */ +#endif + +#ifdef CONFIG_FTSDC021 +# define CONFIG_SDHCI +#endif + +#if defined(CONFIG_FTSDC010) || defined(CONFIG_FTSDC021) +# define CONFIG_MMC +# define CONFIG_CMD_MMC +# define CONFIG_GENERIC_MMC +#endif + +/* + * USB EHCI + */ +#if CONFIG_USB_MAX_CONTROLLER_COUNT > 0 +# define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 +# ifndef CONFIG_USB_HUB_MIN_POWER_ON_DELAY +# define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 500 +# endif +# define CONFIG_USB_EHCI +# define CONFIG_USB_EHCI_FARADAY +# define CONFIG_EHCI_IS_TDI +# define CONFIG_CMD_USB +# define CONFIG_USB_STORAGE +#endif + +/* + * USB Gadget + */ +#ifdef CONFIG_USB_ETHER +# ifndef CONFIG_USBNET_DEV_ADDR +# define CONFIG_USBNET_DEV_ADDR "00:41:71:00:00:55" /* U-Boot */ +# endif +# ifndef CONFIG_USBNET_HOST_ADDR +# define CONFIG_USBNET_HOST_ADDR "00:41:71:00:00:54" /* Host PC */ +# endif +#endif + +#ifdef CONFIG_USBDOWNLOAD_GADGET +# ifndef CONFIG_G_DNL_MANUFACTURER +# define CONFIG_G_DNL_MANUFACTURER "Faraday" +# endif +# ifndef CONFIG_G_DNL_VENDOR_NUM +# define CONFIG_G_DNL_VENDOR_NUM 0x1d50 /* OpenMoko */ +# endif +# ifndef CONFIG_G_DNL_PRODUCT_NUM +# define CONFIG_G_DNL_PRODUCT_NUM 0x5119 +# endif +#endif + +#ifdef CONFIG_DFU_FUNCTION +# ifndef CONFIG_SYS_DFU_DATA_BUF_SIZE +# define CONFIG_SYS_DFU_DATA_BUF_SIZE 4096 +# endif +#endif + +/* + * U-Boot General Configurations + */ +#define CONFIG_LZMA /* Support LZMA */ +#define CONFIG_VERSION_VARIABLE /* Include version env variable */ + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 + +/* Max number of command args */ +#define CONFIG_SYS_MAXARGS 32 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Shell + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "$ " +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +/* + * FAT Filesystem + */ +#if defined(CONFIG_USB_STORAGE) || defined(CONFIG_MMC) +# define CONFIG_DOS_PARTITION +# define CONFIG_CMD_FAT +#endif + +/* + * Linux Kernel Command Line + */ +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG /* support ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS + +/* + * Default Commands + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMD_AUTOSCRIPT /* support autoscript */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* printenv */ +#define CONFIG_CMD_MEMORY /* md mm nm mw ... */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_ELF /* support ELF files */ +#define CONFIG_CMD_LOADB /* xyzModem */ +#ifndef CONFIG_ENV_IS_NOWHERE +# define CONFIG_CMD_SAVEENV /* saveenv */ +#endif + +#endif /* EOF */ -- 1.7.9.5