From mboxrd@z Thu Jan 1 00:00:00 1970 From: vijay.kilari@gmail.com Subject: [PATCH v2 03/15] arm/xen: move gic save and restore registers to gic driver Date: Fri, 4 Apr 2014 17:26:21 +0530 Message-ID: <1396612593-443-4-git-send-email-vijay.kilari@gmail.com> References: <1396612593-443-1-git-send-email-vijay.kilari@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1396612593-443-1-git-send-email-vijay.kilari@gmail.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian.Campbell@citrix.com, julien.grall@linaro.org, stefano.stabellini@eu.citrix.com, stefano.stabellini@citrix.com, xen-devel@lists.xen.org Cc: Prasun.Kapoor@caviumnetworks.com, Vijaya Kumar K , vijay.kilari@gmail.com List-Id: xen-devel@lists.xenproject.org From: Vijaya Kumar K gic saved registers are moved to gic driver. This required structure is allocated at runtime and is saved & restored. Signed-off-by: Vijaya Kumar K --- xen/arch/arm/domain.c | 3 +++ xen/arch/arm/gic.c | 26 +++++++++++++++++--------- xen/include/asm-arm/domain.h | 3 +-- xen/include/asm-arm/gic.h | 8 ++++++++ 4 files changed, 29 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 3d7e685..701298a 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -467,6 +467,9 @@ int vcpu_initialise(struct vcpu *v) v->arch.saved_context.sp = (register_t)v->arch.cpu_info; v->arch.saved_context.pc = (register_t)continue_new_vcpu; + if ( (rc = vcpu_gic_init(v)) != 0 ) + return rc; + /* Idle VCPUs don't need the rest of this setup */ if ( is_idle_vcpu(v) ) return rc; diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 86c52ac..a59118f 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -106,11 +106,11 @@ void gic_save_state(struct vcpu *v) * this call and it only accesses struct vcpu fields that cannot be * accessed simultaneously by another pCPU. */ - for ( i=0; iarch.gic_lr[i] = GICH[GICH_LR + i]; + for ( i = 0; i < nr_lrs; i++ ) + v->arch.gic_state->gic_lr[i] = GICH[GICH_LR + i]; v->arch.lr_mask = this_cpu(lr_mask); - v->arch.gic_apr = GICH[GICH_APR]; - v->arch.gic_vmcr = GICH[GICH_VMCR]; + v->arch.gic_state->gic_apr = GICH[GICH_APR]; + v->arch.gic_state->gic_vmcr = GICH[GICH_VMCR]; /* Disable until next VCPU scheduled */ GICH[GICH_HCR] = 0; isb(); @@ -125,10 +125,10 @@ void gic_restore_state(struct vcpu *v) return; this_cpu(lr_mask) = v->arch.lr_mask; - for ( i=0; iarch.gic_lr[i]; - GICH[GICH_APR] = v->arch.gic_apr; - GICH[GICH_VMCR] = v->arch.gic_vmcr; + for ( i = 0; i < nr_lrs; i++ ) + GICH[GICH_LR + i] = v->arch.gic_state->gic_lr[i]; + GICH[GICH_APR] = v->arch.gic_state->gic_apr; + GICH[GICH_VMCR] = v->arch.gic_state->gic_vmcr; GICH[GICH_HCR] = GICH_HCR_EN; isb(); @@ -975,6 +975,14 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq) } while (1); } +int vcpu_gic_init(struct vcpu *v) +{ + v->arch.gic_state = xzalloc(struct gic_state_data); + if(!v->arch.gic_state) + return -ENOMEM; + return 0; +} + int gicv_setup(struct domain *d) { int ret; @@ -1044,7 +1052,7 @@ void gic_dump_info(struct vcpu *v) printk(" HW_LR[%d]=%x\n", i, GICH[GICH_LR + i]); } else { for ( i = 0; i < nr_lrs; i++ ) - printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]); + printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_state->gic_lr[i]); } list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight ) diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 5b23d07..c51b3cb 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -252,8 +252,7 @@ struct arch_vcpu uint32_t csselr; register_t vmpidr; - uint32_t gic_hcr, gic_vmcr, gic_apr; - uint32_t gic_lr[64]; + struct gic_state_data *gic_state; uint64_t event_mask; uint64_t lr_mask; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index dd7e891..8a28c4a 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -169,12 +169,20 @@ struct vgic_irq_rank { uint32_t itargets[8]; }; +struct gic_state_data { + uint32_t gic_hcr, gic_vmcr; + uint32_t gic_apr; + uint32_t gic_lr[64]; +}; + extern int domain_vgic_init(struct domain *d); extern void domain_vgic_free(struct domain *d); extern int vcpu_vgic_init(struct vcpu *v); extern int vcpu_vgic_free(struct vcpu *v); +extern int vcpu_gic_init(struct vcpu *v); + extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq); extern void vgic_clear_pending_irqs(struct vcpu *v); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); -- 1.7.9.5