[PATCH 00/27] Support new Exynos3250 SoC based on Cortex-A7 dual core

[PATCH 00/27] Support new Exynos3250 SoC based on Cortex-A7 dual core

[Chanwoo Choi]

This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
and provides the best performance features.

This patchset include some patches such as:
- Support secondary CPU of Exynos3250 (cpu up/down)
- Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/pwm/amba
- Support the gpio control for Exynos3250 using pinctrl
- Support the clock control for Exynos3250 using common clk framework

Chanwoo Choi (11):
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250
  ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
  irqchip: Declare cortex-a7's irqchip to initialize gic from dt
  ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
  ARM: dts: exynos3250: Add uart dt node to support seiral ports
  ARM: dts: exynos3250: Add MCT dt node
  ARM: dts: exynos3250: Add ADC dt node to read analog raw data
  ARM: dts: exynos3250: Add CPUs dt node for Exynos3250

Hyunhee Kim (1):
  ARM: dts: exynos3250: Add PMU dt data

Inki Dae (2):
  ARM: dts: exynos3250: Add i2c dt node
  ARM: dts: exynos3250: Add power domain dt nodes

Kyungmin Park (2):
  ARM: EXYNOS: Support secondary CPU boot of Exynos4212
  ARM: dts: exynos3250: Add Mobile Storage Host Card

Tomasz Figa (11):
  pinctrl: exynos: Add driver data for Exynos3250
  clk: samsung: exynos3250: Add clocks using common clock framework
  ARM: dts: exynos3250: Add new exynos3250.dtsi file
  ARM: dts: exynos3250: Add GIC dt node for Exynos3250
  ARM: dts: exynos3250: Add pin control device tree data
  ARM: dts: exynos3250: Add device tree nodes for clock controllers
  ARM: dts: exynos3250: Move definitions of external clocks to SoC dtsi
  ARM: dts: exynos3250: Add amba and pdma dt node
  ARM: dts: exynos3250: Add spi dt node to support spi bus
  ARM: dts: exynos3250: Add pwm dt node to support PWM Timer
  ARM: dts: exynos3250: Add RTC dt node

 arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 ++++++++++++++++++
 arch/arm/boot/dts/exynos3250.dtsi         | 410 ++++++++++++++++
 arch/arm/mach-exynos/Kconfig              |  22 +
 arch/arm/mach-exynos/exynos.c             |  18 +
 arch/arm/mach-exynos/firmware.c           |  17 +-
 arch/arm/mach-exynos/hotplug.c            |  13 +-
 arch/arm/mach-exynos/include/mach/map.h   |   2 +
 arch/arm/plat-samsung/include/plat/cpu.h  |  10 +
 drivers/clk/samsung/Makefile              |   1 +
 drivers/clk/samsung/clk-exynos3250.c      | 785 ++++++++++++++++++++++++++++++
 drivers/irqchip/irq-gic.c                 |   1 +
 drivers/pinctrl/pinctrl-exynos.c          |  67 +++
 drivers/pinctrl/pinctrl-samsung.c         |   2 +
 drivers/pinctrl/pinctrl-samsung.h         |   1 +
 include/dt-bindings/clock/exynos3250.h    | 256 ++++++++++
 15 files changed, 2077 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
 create mode 100644 drivers/clk/samsung/clk-exynos3250.c
 create mode 100644 include/dt-bindings/clock/exynos3250.h

-- 
1.8.0

[PATCH 00/27] Support new Exynos3250 SoC based on Cortex-A7 dual core

[Chanwoo Choi]

This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
and provides the best performance features.

This patchset include some patches such as:
- Support secondary CPU of Exynos3250 (cpu up/down)
- Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/pwm/amba
- Support the gpio control for Exynos3250 using pinctrl
- Support the clock control for Exynos3250 using common clk framework

Chanwoo Choi (11):
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250
  ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
  irqchip: Declare cortex-a7's irqchip to initialize gic from dt
  ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
  ARM: dts: exynos3250: Add uart dt node to support seiral ports
  ARM: dts: exynos3250: Add MCT dt node
  ARM: dts: exynos3250: Add ADC dt node to read analog raw data
  ARM: dts: exynos3250: Add CPUs dt node for Exynos3250

Hyunhee Kim (1):
  ARM: dts: exynos3250: Add PMU dt data

Inki Dae (2):
  ARM: dts: exynos3250: Add i2c dt node
  ARM: dts: exynos3250: Add power domain dt nodes

Kyungmin Park (2):
  ARM: EXYNOS: Support secondary CPU boot of Exynos4212
  ARM: dts: exynos3250: Add Mobile Storage Host Card

Tomasz Figa (11):
  pinctrl: exynos: Add driver data for Exynos3250
  clk: samsung: exynos3250: Add clocks using common clock framework
  ARM: dts: exynos3250: Add new exynos3250.dtsi file
  ARM: dts: exynos3250: Add GIC dt node for Exynos3250
  ARM: dts: exynos3250: Add pin control device tree data
  ARM: dts: exynos3250: Add device tree nodes for clock controllers
  ARM: dts: exynos3250: Move definitions of external clocks to SoC dtsi
  ARM: dts: exynos3250: Add amba and pdma dt node
  ARM: dts: exynos3250: Add spi dt node to support spi bus
  ARM: dts: exynos3250: Add pwm dt node to support PWM Timer
  ARM: dts: exynos3250: Add RTC dt node

 arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 ++++++++++++++++++
 arch/arm/boot/dts/exynos3250.dtsi         | 410 ++++++++++++++++
 arch/arm/mach-exynos/Kconfig              |  22 +
 arch/arm/mach-exynos/exynos.c             |  18 +
 arch/arm/mach-exynos/firmware.c           |  17 +-
 arch/arm/mach-exynos/hotplug.c            |  13 +-
 arch/arm/mach-exynos/include/mach/map.h   |   2 +
 arch/arm/plat-samsung/include/plat/cpu.h  |  10 +
 drivers/clk/samsung/Makefile              |   1 +
 drivers/clk/samsung/clk-exynos3250.c      | 785 ++++++++++++++++++++++++++++++
 drivers/irqchip/irq-gic.c                 |   1 +
 drivers/pinctrl/pinctrl-exynos.c          |  67 +++
 drivers/pinctrl/pinctrl-samsung.c         |   2 +
 drivers/pinctrl/pinctrl-samsung.h         |   1 +
 include/dt-bindings/clock/exynos3250.h    | 256 ++++++++++
 15 files changed, 2077 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
 create mode 100644 drivers/clk/samsung/clk-exynos3250.c
 create mode 100644 include/dt-bindings/clock/exynos3250.h

-- 
1.8.0

[PATCH 00/27] Support new Exynos3250 SoC based on Cortex-A7 dual core

[Chanwoo Choi]

This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
and provides the best performance features.

This patchset include some patches such as:
- Support secondary CPU of Exynos3250 (cpu up/down)
- Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/pwm/amba
- Support the gpio control for Exynos3250 using pinctrl
- Support the clock control for Exynos3250 using common clk framework

Chanwoo Choi (11):
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250
  ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
  irqchip: Declare cortex-a7's irqchip to initialize gic from dt
  ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
  ARM: dts: exynos3250: Add uart dt node to support seiral ports
  ARM: dts: exynos3250: Add MCT dt node
  ARM: dts: exynos3250: Add ADC dt node to read analog raw data
  ARM: dts: exynos3250: Add CPUs dt node for Exynos3250

Hyunhee Kim (1):
  ARM: dts: exynos3250: Add PMU dt data

Inki Dae (2):
  ARM: dts: exynos3250: Add i2c dt node
  ARM: dts: exynos3250: Add power domain dt nodes

Kyungmin Park (2):
  ARM: EXYNOS: Support secondary CPU boot of Exynos4212
  ARM: dts: exynos3250: Add Mobile Storage Host Card

Tomasz Figa (11):
  pinctrl: exynos: Add driver data for Exynos3250
  clk: samsung: exynos3250: Add clocks using common clock framework
  ARM: dts: exynos3250: Add new exynos3250.dtsi file
  ARM: dts: exynos3250: Add GIC dt node for Exynos3250
  ARM: dts: exynos3250: Add pin control device tree data
  ARM: dts: exynos3250: Add device tree nodes for clock controllers
  ARM: dts: exynos3250: Move definitions of external clocks to SoC dtsi
  ARM: dts: exynos3250: Add amba and pdma dt node
  ARM: dts: exynos3250: Add spi dt node to support spi bus
  ARM: dts: exynos3250: Add pwm dt node to support PWM Timer
  ARM: dts: exynos3250: Add RTC dt node

 arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 ++++++++++++++++++
 arch/arm/boot/dts/exynos3250.dtsi         | 410 ++++++++++++++++
 arch/arm/mach-exynos/Kconfig              |  22 +
 arch/arm/mach-exynos/exynos.c             |  18 +
 arch/arm/mach-exynos/firmware.c           |  17 +-
 arch/arm/mach-exynos/hotplug.c            |  13 +-
 arch/arm/mach-exynos/include/mach/map.h   |   2 +
 arch/arm/plat-samsung/include/plat/cpu.h  |  10 +
 drivers/clk/samsung/Makefile              |   1 +
 drivers/clk/samsung/clk-exynos3250.c      | 785 ++++++++++++++++++++++++++++++
 drivers/irqchip/irq-gic.c                 |   1 +
 drivers/pinctrl/pinctrl-exynos.c          |  67 +++
 drivers/pinctrl/pinctrl-samsung.c         |   2 +
 drivers/pinctrl/pinctrl-samsung.h         |   1 +
 include/dt-bindings/clock/exynos3250.h    | 256 ++++++++++
 15 files changed, 2077 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
 create mode 100644 drivers/clk/samsung/clk-exynos3250.c
 create mode 100644 include/dt-bindings/clock/exynos3250.h

-- 
1.8.0

[PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Chanwoo Choi]

This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
dual cores and has a target speed of 1.0GHz.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
 arch/arm/mach-exynos/exynos.c            |  1 +
 arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
 3 files changed, 33 insertions(+)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18..6da8a68 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,6 +11,17 @@ if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"
 
+config ARCH_EXYNOS3
+	bool "SAMSUNG EXYNOS3"
+	select ARM_AMBA
+	select CLKSRC_OF
+	select HAVE_ARM_SCU if SMP
+	select HAVE_SMP
+	select PINCTRL
+	select PM_GENERIC_DOMAINS if PM_RUNTIME
+	help
+	  Samsung EXYNOS3 SoCs based systems
+
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
 	default y
@@ -41,6 +52,17 @@ config ARCH_EXYNOS5
 
 comment "EXYNOS SoCs"
 
+config SOC_EXYNOS3250
+	bool "SAMSUNG EXYNOS3250"
+	default y
+	depends on ARCH_EXYNOS3
+	select ARCH_HAS_BANDGAP
+	select ARM_CPU_SUSPEND if PM
+	select PINCTRL_EXYNOS
+	select SAMSUNG_DMADEV
+	help
+	  Enable EXYNOS3250 CPU support
+
 config CPU_EXYNOS4210
 	bool "SAMSUNG EXYNOS4210"
 	default y
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b32a907..b134868 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -370,6 +370,7 @@ static void __init exynos_dt_machine_init(void)
 }
 
 static char const *exynos_dt_compat[] __initconst = {
+	"samsung,exynos3250",
 	"samsung,exynos4",
 	"samsung,exynos4210",
 	"samsung,exynos4212",
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8d..3d808f6b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,6 +43,9 @@ extern unsigned long samsung_cpu_id;
 #define S5PV210_CPU_ID		0x43110000
 #define S5PV210_CPU_MASK	0xFFFFF000
 
+#define EXYNOS3250_SOC_ID       0xE3472000
+#define EXYNOS3_SOC_MASK        0xFFFFF000
+
 #define EXYNOS4210_CPU_ID	0x43210000
 #define EXYNOS4212_CPU_ID	0x43220000
 #define EXYNOS4412_CPU_ID	0xE4412200
@@ -68,6 +71,7 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
 IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
+IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
@@ -126,6 +130,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s5pv210()	0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS3250)
+# define soc_is_exynos3250()    is_samsung_exynos3250()
+#else
+# define soc_is_exynos3250()    0
+#endif
+
 #if defined(CONFIG_CPU_EXYNOS4210)
 # define soc_is_exynos4210()	is_samsung_exynos4210()
 #else
-- 
1.8.0

[PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Chanwoo Choi]

This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
dual cores and has a target speed of 1.0GHz.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
 arch/arm/mach-exynos/exynos.c            |  1 +
 arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
 3 files changed, 33 insertions(+)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18..6da8a68 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,6 +11,17 @@ if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"
 
+config ARCH_EXYNOS3
+	bool "SAMSUNG EXYNOS3"
+	select ARM_AMBA
+	select CLKSRC_OF
+	select HAVE_ARM_SCU if SMP
+	select HAVE_SMP
+	select PINCTRL
+	select PM_GENERIC_DOMAINS if PM_RUNTIME
+	help
+	  Samsung EXYNOS3 SoCs based systems
+
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
 	default y
@@ -41,6 +52,17 @@ config ARCH_EXYNOS5
 
 comment "EXYNOS SoCs"
 
+config SOC_EXYNOS3250
+	bool "SAMSUNG EXYNOS3250"
+	default y
+	depends on ARCH_EXYNOS3
+	select ARCH_HAS_BANDGAP
+	select ARM_CPU_SUSPEND if PM
+	select PINCTRL_EXYNOS
+	select SAMSUNG_DMADEV
+	help
+	  Enable EXYNOS3250 CPU support
+
 config CPU_EXYNOS4210
 	bool "SAMSUNG EXYNOS4210"
 	default y
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b32a907..b134868 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -370,6 +370,7 @@ static void __init exynos_dt_machine_init(void)
 }
 
 static char const *exynos_dt_compat[] __initconst = {
+	"samsung,exynos3250",
 	"samsung,exynos4",
 	"samsung,exynos4210",
 	"samsung,exynos4212",
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8d..3d808f6b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,6 +43,9 @@ extern unsigned long samsung_cpu_id;
 #define S5PV210_CPU_ID		0x43110000
 #define S5PV210_CPU_MASK	0xFFFFF000
 
+#define EXYNOS3250_SOC_ID       0xE3472000
+#define EXYNOS3_SOC_MASK        0xFFFFF000
+
 #define EXYNOS4210_CPU_ID	0x43210000
 #define EXYNOS4212_CPU_ID	0x43220000
 #define EXYNOS4412_CPU_ID	0xE4412200
@@ -68,6 +71,7 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
 IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
+IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
@@ -126,6 +130,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s5pv210()	0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS3250)
+# define soc_is_exynos3250()    is_samsung_exynos3250()
+#else
+# define soc_is_exynos3250()    0
+#endif
+
 #if defined(CONFIG_CPU_EXYNOS4210)
 # define soc_is_exynos4210()	is_samsung_exynos4210()
 #else
-- 
1.8.0

[PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Chanwoo Choi]

This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
dual cores and has a target speed of 1.0GHz.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
 arch/arm/mach-exynos/exynos.c            |  1 +
 arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
 3 files changed, 33 insertions(+)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18..6da8a68 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,6 +11,17 @@ if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"
 
+config ARCH_EXYNOS3
+	bool "SAMSUNG EXYNOS3"
+	select ARM_AMBA
+	select CLKSRC_OF
+	select HAVE_ARM_SCU if SMP
+	select HAVE_SMP
+	select PINCTRL
+	select PM_GENERIC_DOMAINS if PM_RUNTIME
+	help
+	  Samsung EXYNOS3 SoCs based systems
+
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
 	default y
@@ -41,6 +52,17 @@ config ARCH_EXYNOS5
 
 comment "EXYNOS SoCs"
 
+config SOC_EXYNOS3250
+	bool "SAMSUNG EXYNOS3250"
+	default y
+	depends on ARCH_EXYNOS3
+	select ARCH_HAS_BANDGAP
+	select ARM_CPU_SUSPEND if PM
+	select PINCTRL_EXYNOS
+	select SAMSUNG_DMADEV
+	help
+	  Enable EXYNOS3250 CPU support
+
 config CPU_EXYNOS4210
 	bool "SAMSUNG EXYNOS4210"
 	default y
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b32a907..b134868 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -370,6 +370,7 @@ static void __init exynos_dt_machine_init(void)
 }
 
 static char const *exynos_dt_compat[] __initconst = {
+	"samsung,exynos3250",
 	"samsung,exynos4",
 	"samsung,exynos4210",
 	"samsung,exynos4212",
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8d..3d808f6b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,6 +43,9 @@ extern unsigned long samsung_cpu_id;
 #define S5PV210_CPU_ID		0x43110000
 #define S5PV210_CPU_MASK	0xFFFFF000
 
+#define EXYNOS3250_SOC_ID       0xE3472000
+#define EXYNOS3_SOC_MASK        0xFFFFF000
+
 #define EXYNOS4210_CPU_ID	0x43210000
 #define EXYNOS4212_CPU_ID	0x43220000
 #define EXYNOS4412_CPU_ID	0xE4412200
@@ -68,6 +71,7 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
 IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
+IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
@@ -126,6 +130,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s5pv210()	0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS3250)
+# define soc_is_exynos3250()    is_samsung_exynos3250()
+#else
+# define soc_is_exynos3250()    0
+#endif
+
 #if defined(CONFIG_CPU_EXYNOS4210)
 # define soc_is_exynos4210()	is_samsung_exynos4210()
 #else
-- 
1.8.0

[PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250

[Chanwoo Choi]

The non-secure SYSRAM is used for secondary CPU bring-up. This patch add
IO mapping for non-scure SYSRAM.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/exynos.c           | 12 ++++++++++++
 arch/arm/mach-exynos/include/mach/map.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b134868..cad3bfd 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -35,6 +35,15 @@
 #define L2_AUX_VAL 0x7C470001
 #define L2_AUX_MASK 0xC200ffff
 
+static struct map_desc exynos3250_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
+		.pfn		= __phys_to_pfn(EXYNOS3_PA_SYSRAM_NS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
 static struct map_desc exynos4_iodesc[] __initdata = {
 	{
 		.virtual	= (unsigned long)S3C_VA_SYS,
@@ -275,6 +284,9 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
  */
 static void __init exynos_map_io(void)
 {
+	if (soc_is_exynos3250())
+		iotable_init(exynos3250_iodesc, ARRAY_SIZE(exynos3250_iodesc));
+
 	if (soc_is_exynos4())
 		iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..a53981b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -26,6 +26,7 @@
 #define EXYNOS4_PA_SYSRAM0		0x02025000
 #define EXYNOS4_PA_SYSRAM1		0x02020000
 #define EXYNOS5_PA_SYSRAM		0x02020000
+#define EXYNOS3_PA_SYSRAM_NS		0x0205F000
 #define EXYNOS4210_PA_SYSRAM_NS		0x0203F000
 #define EXYNOS4x12_PA_SYSRAM_NS		0x0204F000
 #define EXYNOS5250_PA_SYSRAM_NS		0x0204F000
-- 
1.8.0

[PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250

[Chanwoo Choi]

The non-secure SYSRAM is used for secondary CPU bring-up. This patch add
IO mapping for non-scure SYSRAM.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/exynos.c           | 12 ++++++++++++
 arch/arm/mach-exynos/include/mach/map.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b134868..cad3bfd 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -35,6 +35,15 @@
 #define L2_AUX_VAL 0x7C470001
 #define L2_AUX_MASK 0xC200ffff
 
+static struct map_desc exynos3250_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
+		.pfn		= __phys_to_pfn(EXYNOS3_PA_SYSRAM_NS),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
 static struct map_desc exynos4_iodesc[] __initdata = {
 	{
 		.virtual	= (unsigned long)S3C_VA_SYS,
@@ -275,6 +284,9 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
  */
 static void __init exynos_map_io(void)
 {
+	if (soc_is_exynos3250())
+		iotable_init(exynos3250_iodesc, ARRAY_SIZE(exynos3250_iodesc));
+
 	if (soc_is_exynos4())
 		iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..a53981b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -26,6 +26,7 @@
 #define EXYNOS4_PA_SYSRAM0		0x02025000
 #define EXYNOS4_PA_SYSRAM1		0x02020000
 #define EXYNOS5_PA_SYSRAM		0x02020000
+#define EXYNOS3_PA_SYSRAM_NS		0x0205F000
 #define EXYNOS4210_PA_SYSRAM_NS		0x0203F000
 #define EXYNOS4x12_PA_SYSRAM_NS		0x0204F000
 #define EXYNOS5250_PA_SYSRAM_NS		0x0204F000
-- 
1.8.0

[PATCH 03/27] ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

[Chanwoo Choi]

This patch add memory mapping for PMU (Power Management Unit) which is used
for power control of Exynos3250.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/exynos.c           | 5 +++++
 arch/arm/mach-exynos/include/mach/map.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index cad3bfd..628e4b1 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -41,6 +41,11 @@ static struct map_desc exynos3250_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS3_PA_SYSRAM_NS),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_PMU,
+		.pfn		= __phys_to_pfn(EXYNOS3_PA_PMU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
 	},
 };
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index a53981b..4aea694 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -36,6 +36,7 @@
 #define EXYNOS4_PA_SYSCON		0x10010000
 #define EXYNOS5_PA_SYSCON		0x10050100
 
+#define EXYNOS3_PA_PMU			0x10020000
 #define EXYNOS4_PA_PMU			0x10020000
 #define EXYNOS5_PA_PMU			0x10040000
 
-- 
1.8.0

[PATCH 03/27] ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

[Chanwoo Choi]

This patch add memory mapping for PMU (Power Management Unit) which is used
for power control of Exynos3250.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/exynos.c           | 5 +++++
 arch/arm/mach-exynos/include/mach/map.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index cad3bfd..628e4b1 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -41,6 +41,11 @@ static struct map_desc exynos3250_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS3_PA_SYSRAM_NS),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_PMU,
+		.pfn		= __phys_to_pfn(EXYNOS3_PA_PMU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
 	},
 };
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index a53981b..4aea694 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -36,6 +36,7 @@
 #define EXYNOS4_PA_SYSCON		0x10010000
 #define EXYNOS5_PA_SYSCON		0x10050100
 
+#define EXYNOS3_PA_PMU			0x10020000
 #define EXYNOS4_PA_PMU			0x10020000
 #define EXYNOS5_PA_PMU			0x10040000
 
-- 
1.8.0

[PATCH 04/27] ARM: EXYNOS: Support secondary CPU boot of Exynos4212

[Chanwoo Choi]

From: Kyungmin Park <kyungmin.park@samsung.com>

This patch fix the offset of CPU boot address and change parameter of smc call
of SMC_CMD_CPU1BOOT command for Exynos4212.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/firmware.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 932129e..91a911d 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -18,6 +18,8 @@
 
 #include <mach/map.h>
 
+#include <plat/cpu.h>
+
 #include "smc.h"
 
 static int exynos_do_idle(void)
@@ -28,14 +30,22 @@ static int exynos_do_idle(void)
 
 static int exynos_cpu_boot(int cpu)
 {
-	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
+	if (soc_is_exynos4212())
+		exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
+	else
+		exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
 	return 0;
 }
 
 static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
-	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
+	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
 
+	if (soc_is_exynos4212())
+		goto out;
+	else
+		boot_reg += 4*cpu;
+out:
 	__raw_writel(boot_addr, boot_reg);
 	return 0;
 }
-- 
1.8.0

[PATCH 04/27] ARM: EXYNOS: Support secondary CPU boot of Exynos4212

[Chanwoo Choi]

From: Kyungmin Park <kyungmin.park@samsung.com>

This patch fix the offset of CPU boot address and change parameter of smc call
of SMC_CMD_CPU1BOOT command for Exynos4212.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/firmware.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 932129e..91a911d 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -18,6 +18,8 @@
 
 #include <mach/map.h>
 
+#include <plat/cpu.h>
+
 #include "smc.h"
 
 static int exynos_do_idle(void)
@@ -28,14 +30,22 @@ static int exynos_do_idle(void)
 
 static int exynos_cpu_boot(int cpu)
 {
-	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
+	if (soc_is_exynos4212())
+		exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
+	else
+		exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
 	return 0;
 }
 
 static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
-	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
+	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
 
+	if (soc_is_exynos4212())
+		goto out;
+	else
+		boot_reg += 4*cpu;
+out:
 	__raw_writel(boot_addr, boot_reg);
 	return 0;
 }
-- 
1.8.0

[PATCH 05/27] ARM: EXYNOS: Support secondary CPU boot of Exynos3250

[Chanwoo Choi]

This patch fix the offset of CPU boot address and don't operate smc call
of SMC_CMD_CPU1BOOT command for Exynos3250.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/firmware.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 91a911d..8350007 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -30,10 +30,13 @@ static int exynos_do_idle(void)
 
 static int exynos_cpu_boot(int cpu)
 {
-	if (soc_is_exynos4212())
+	if (soc_is_exynos3250())
+		goto out;
+	else if (soc_is_exynos4212())
 		exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
 	else
 		exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
+out:
 	return 0;
 }
 
@@ -41,7 +44,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
 	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
 
-	if (soc_is_exynos4212())
+	if (soc_is_exynos4212() || soc_is_exynos3250())
 		goto out;
 	else
 		boot_reg += 4*cpu;
-- 
1.8.0

[PATCH 05/27] ARM: EXYNOS: Support secondary CPU boot of Exynos3250

[Chanwoo Choi]

This patch fix the offset of CPU boot address and don't operate smc call
of SMC_CMD_CPU1BOOT command for Exynos3250.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/firmware.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 91a911d..8350007 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -30,10 +30,13 @@ static int exynos_do_idle(void)
 
 static int exynos_cpu_boot(int cpu)
 {
-	if (soc_is_exynos4212())
+	if (soc_is_exynos3250())
+		goto out;
+	else if (soc_is_exynos4212())
 		exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
 	else
 		exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
+out:
 	return 0;
 }
 
@@ -41,7 +44,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
 	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
 
-	if (soc_is_exynos4212())
+	if (soc_is_exynos4212() || soc_is_exynos3250())
 		goto out;
 	else
 		boot_reg += 4*cpu;
-- 
1.8.0

[PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

This patch decide proper lowpower mode of either a15 or a9 according to own ID
from Main ID register.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..36d3db6 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
 	int primary_part = 0;
 
 	/*
-	 * we're ready for shutdown now, so do it.
-	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
+	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
+	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
 	 * number by reading the Main ID register and then perform the
 	 * appropriate sequence for entering low power.
 	 */
 	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
-	if ((primary_part & 0xfff0) == 0xc0f0)
+
+	/*
+	 * Main ID register of Cortex series
+	 * - Cortex-a7  : 0x410F_C07x
+	 * - Cortex-a15 : 0x410F_C0Fx
+	 */
+	primary_part = primary_part & 0xfff0;
+	if (primary_part == 0xc0f0 || primary_part == 0xc070)
 		cpu_enter_lowpower_a15();
 	else
 		cpu_enter_lowpower_a9();
-- 
1.8.0

[PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

This patch decide proper lowpower mode of either a15 or a9 according to own ID
from Main ID register.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..36d3db6 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
 	int primary_part = 0;
 
 	/*
-	 * we're ready for shutdown now, so do it.
-	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
+	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
+	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
 	 * number by reading the Main ID register and then perform the
 	 * appropriate sequence for entering low power.
 	 */
 	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
-	if ((primary_part & 0xfff0) == 0xc0f0)
+
+	/*
+	 * Main ID register of Cortex series
+	 * - Cortex-a7  : 0x410F_C07x
+	 * - Cortex-a15 : 0x410F_C0Fx
+	 */
+	primary_part = primary_part & 0xfff0;
+	if (primary_part == 0xc0f0 || primary_part == 0xc070)
 		cpu_enter_lowpower_a15();
 	else
 		cpu_enter_lowpower_a9();
-- 
1.8.0

[PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

This patch decide proper lowpower mode of either a15 or a9 according to own ID
from Main ID register.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..36d3db6 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
 	int primary_part = 0;
 
 	/*
-	 * we're ready for shutdown now, so do it.
-	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
+	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
+	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
 	 * number by reading the Main ID register and then perform the
 	 * appropriate sequence for entering low power.
 	 */
 	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
-	if ((primary_part & 0xfff0) == 0xc0f0)
+
+	/*
+	 * Main ID register of Cortex series
+	 * - Cortex-a7  : 0x410F_C07x
+	 * - Cortex-a15 : 0x410F_C0Fx
+	 */
+	primary_part = primary_part & 0xfff0;
+	if (primary_part == 0xc0f0 || primary_part == 0xc070)
 		cpu_enter_lowpower_a15();
 	else
 		cpu_enter_lowpower_a9();
-- 
1.8.0

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Chanwoo Choi]

This patch declare coretex-a7's irqchip to initialze gic from dt
with "arm,cortex-a7-gic" data.

Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/irqchip/irq-gic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 4300b66..8e906e4 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 }
 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
+IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
 
-- 
1.8.0

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Chanwoo Choi]

This patch declare coretex-a7's irqchip to initialze gic from dt
with "arm,cortex-a7-gic" data.

Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/irqchip/irq-gic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 4300b66..8e906e4 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 }
 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
+IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
 
-- 
1.8.0

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Chanwoo Choi]

This patch declare coretex-a7's irqchip to initialze gic from dt
with "arm,cortex-a7-gic" data.

Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/irqchip/irq-gic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 4300b66..8e906e4 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 }
 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
+IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
 
-- 
1.8.0

[PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Chanwoo Choi]

From: Tomasz Figa <t.figa@samsung.com>

This patch adds driver data (bank list and EINT layout) for Exynos3250
to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
ports. There are 23 general port groups.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/pinctrl/pinctrl-exynos.c  | 67 +++++++++++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.c |  2 ++
 drivers/pinctrl/pinctrl-samsung.h |  1 +
 3 files changed, 70 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 07c8130..9609c23 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -718,6 +718,73 @@ struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
 	},
 };
 
+/* pin banks of exynos3250 pin-controller 0 */
+static struct samsung_pin_bank exynos3250_pin_banks0[] = {
+	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+	EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
+	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb",  0x08),
+	EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
+	EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
+	EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
+	EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
+};
+
+/* pin banks of exynos3250 pin-controller 1 */
+static struct samsung_pin_bank exynos3250_pin_banks1[] = {
+	EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
+	EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
+	EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
+	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
+	EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
+	EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
+	EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
+	EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
+	EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
+	EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
+	EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
+	EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
+ * two gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
+	{
+		/* pin-controller instance 0 data */
+		.pin_banks	= exynos3250_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos3250_pin_banks0),
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
+		.label		= "exynos3250-gpio-ctrl0",
+	}, {
+		/* pin-controller instance 1 data */
+		.pin_banks	= exynos3250_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos3250_pin_banks1),
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.weint_con	= EXYNOS_WKUP_ECON_OFFSET,
+		.weint_mask	= EXYNOS_WKUP_EMASK_OFFSET,
+		.weint_pend	= EXYNOS_WKUP_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
+		.label		= "exynos3250-gpio-ctrl1",
+	},
+};
+
 /* pin banks of exynos4210 pin-controller 0 */
 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
 	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 0324d4c..3e61d0f 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1114,6 +1114,8 @@ static struct syscore_ops samsung_pinctrl_syscore_ops = {
 
 static const struct of_device_id samsung_pinctrl_dt_match[] = {
 #ifdef CONFIG_PINCTRL_EXYNOS
+	{ .compatible = "samsung,exynos3250-pinctrl",
+		.data = (void *)exynos3250_pin_ctrl },
 	{ .compatible = "samsung,exynos4210-pinctrl",
 		.data = (void *)exynos4210_pin_ctrl },
 	{ .compatible = "samsung,exynos4x12-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index bab9c21..b3e41fa 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -251,6 +251,7 @@ struct samsung_pmx_func {
 };
 
 /* list of all exported SoC specific data */
+extern struct samsung_pin_ctrl exynos3250_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
-- 
1.8.0

[PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Chanwoo Choi]

From: Tomasz Figa <t.figa@samsung.com>

This patch adds driver data (bank list and EINT layout) for Exynos3250
to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
ports. There are 23 general port groups.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/pinctrl/pinctrl-exynos.c  | 67 +++++++++++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.c |  2 ++
 drivers/pinctrl/pinctrl-samsung.h |  1 +
 3 files changed, 70 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 07c8130..9609c23 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -718,6 +718,73 @@ struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
 	},
 };
 
+/* pin banks of exynos3250 pin-controller 0 */
+static struct samsung_pin_bank exynos3250_pin_banks0[] = {
+	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+	EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
+	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb",  0x08),
+	EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
+	EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
+	EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
+	EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
+};
+
+/* pin banks of exynos3250 pin-controller 1 */
+static struct samsung_pin_bank exynos3250_pin_banks1[] = {
+	EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
+	EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
+	EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
+	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
+	EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
+	EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
+	EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
+	EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
+	EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
+	EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
+	EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
+	EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
+	EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
+ * two gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
+	{
+		/* pin-controller instance 0 data */
+		.pin_banks	= exynos3250_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos3250_pin_banks0),
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
+		.label		= "exynos3250-gpio-ctrl0",
+	}, {
+		/* pin-controller instance 1 data */
+		.pin_banks	= exynos3250_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos3250_pin_banks1),
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.weint_con	= EXYNOS_WKUP_ECON_OFFSET,
+		.weint_mask	= EXYNOS_WKUP_EMASK_OFFSET,
+		.weint_pend	= EXYNOS_WKUP_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
+		.label		= "exynos3250-gpio-ctrl1",
+	},
+};
+
 /* pin banks of exynos4210 pin-controller 0 */
 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
 	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 0324d4c..3e61d0f 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1114,6 +1114,8 @@ static struct syscore_ops samsung_pinctrl_syscore_ops = {
 
 static const struct of_device_id samsung_pinctrl_dt_match[] = {
 #ifdef CONFIG_PINCTRL_EXYNOS
+	{ .compatible = "samsung,exynos3250-pinctrl",
+		.data = (void *)exynos3250_pin_ctrl },
 	{ .compatible = "samsung,exynos4210-pinctrl",
 		.data = (void *)exynos4210_pin_ctrl },
 	{ .compatible = "samsung,exynos4x12-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index bab9c21..b3e41fa 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -251,6 +251,7 @@ struct samsung_pmx_func {
 };
 
 /* list of all exported SoC specific data */
+extern struct samsung_pin_ctrl exynos3250_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
-- 
1.8.0

Re: [PATCH 00/27] Support new Exynos3250 SoC based on Cortex-A7 dual core

[Chanwoo Choi]

Dear all,

Ignore this patchset because this patchset don't include all of patches.
I'll send this patchset again right now.

Sorry for my mistake.

Best Regards,
Chanwoo Choi

On 04/10/2014 06:28 PM, Chanwoo Choi wrote:
> This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
> Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
> for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
> and provides the best performance features.
> 
> This patchset include some patches such as:
> - Support secondary CPU of Exynos3250 (cpu up/down)
> - Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/pwm/amba
> - Support the gpio control for Exynos3250 using pinctrl
> - Support the clock control for Exynos3250 using common clk framework
> 
> Chanwoo Choi (11):
>   ARM: EXYNOS: Add Exynos3250 SoC ID
>   ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250
>   ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
>   ARM: EXYNOS: Support secondary CPU boot of Exynos3250
>   ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
>   irqchip: Declare cortex-a7's irqchip to initialize gic from dt
>   ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
>   ARM: dts: exynos3250: Add uart dt node to support seiral ports
>   ARM: dts: exynos3250: Add MCT dt node
>   ARM: dts: exynos3250: Add ADC dt node to read analog raw data
>   ARM: dts: exynos3250: Add CPUs dt node for Exynos3250
> 
> Hyunhee Kim (1):
>   ARM: dts: exynos3250: Add PMU dt data
> 
> Inki Dae (2):
>   ARM: dts: exynos3250: Add i2c dt node
>   ARM: dts: exynos3250: Add power domain dt nodes
> 
> Kyungmin Park (2):
>   ARM: EXYNOS: Support secondary CPU boot of Exynos4212
>   ARM: dts: exynos3250: Add Mobile Storage Host Card
> 
> Tomasz Figa (11):
>   pinctrl: exynos: Add driver data for Exynos3250
>   clk: samsung: exynos3250: Add clocks using common clock framework
>   ARM: dts: exynos3250: Add new exynos3250.dtsi file
>   ARM: dts: exynos3250: Add GIC dt node for Exynos3250
>   ARM: dts: exynos3250: Add pin control device tree data
>   ARM: dts: exynos3250: Add device tree nodes for clock controllers
>   ARM: dts: exynos3250: Move definitions of external clocks to SoC dtsi
>   ARM: dts: exynos3250: Add amba and pdma dt node
>   ARM: dts: exynos3250: Add spi dt node to support spi bus
>   ARM: dts: exynos3250: Add pwm dt node to support PWM Timer
>   ARM: dts: exynos3250: Add RTC dt node
> 
>  arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 ++++++++++++++++++
>  arch/arm/boot/dts/exynos3250.dtsi         | 410 ++++++++++++++++
>  arch/arm/mach-exynos/Kconfig              |  22 +
>  arch/arm/mach-exynos/exynos.c             |  18 +
>  arch/arm/mach-exynos/firmware.c           |  17 +-
>  arch/arm/mach-exynos/hotplug.c            |  13 +-
>  arch/arm/mach-exynos/include/mach/map.h   |   2 +
>  arch/arm/plat-samsung/include/plat/cpu.h  |  10 +
>  drivers/clk/samsung/Makefile              |   1 +
>  drivers/clk/samsung/clk-exynos3250.c      | 785 ++++++++++++++++++++++++++++++
>  drivers/irqchip/irq-gic.c                 |   1 +
>  drivers/pinctrl/pinctrl-exynos.c          |  67 +++
>  drivers/pinctrl/pinctrl-samsung.c         |   2 +
>  drivers/pinctrl/pinctrl-samsung.h         |   1 +
>  include/dt-bindings/clock/exynos3250.h    | 256 ++++++++++
>  15 files changed, 2077 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>  create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>  create mode 100644 drivers/clk/samsung/clk-exynos3250.c
>  create mode 100644 include/dt-bindings/clock/exynos3250.h
> 

[PATCH 00/27] Support new Exynos3250 SoC based on Cortex-A7 dual core

[Chanwoo Choi]

Dear all,

Ignore this patchset because this patchset don't include all of patches.
I'll send this patchset again right now.

Sorry for my mistake.

Best Regards,
Chanwoo Choi

On 04/10/2014 06:28 PM, Chanwoo Choi wrote:
> This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
> Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
> for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
> and provides the best performance features.
> 
> This patchset include some patches such as:
> - Support secondary CPU of Exynos3250 (cpu up/down)
> - Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/pwm/amba
> - Support the gpio control for Exynos3250 using pinctrl
> - Support the clock control for Exynos3250 using common clk framework
> 
> Chanwoo Choi (11):
>   ARM: EXYNOS: Add Exynos3250 SoC ID
>   ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250
>   ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
>   ARM: EXYNOS: Support secondary CPU boot of Exynos3250
>   ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
>   irqchip: Declare cortex-a7's irqchip to initialize gic from dt
>   ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
>   ARM: dts: exynos3250: Add uart dt node to support seiral ports
>   ARM: dts: exynos3250: Add MCT dt node
>   ARM: dts: exynos3250: Add ADC dt node to read analog raw data
>   ARM: dts: exynos3250: Add CPUs dt node for Exynos3250
> 
> Hyunhee Kim (1):
>   ARM: dts: exynos3250: Add PMU dt data
> 
> Inki Dae (2):
>   ARM: dts: exynos3250: Add i2c dt node
>   ARM: dts: exynos3250: Add power domain dt nodes
> 
> Kyungmin Park (2):
>   ARM: EXYNOS: Support secondary CPU boot of Exynos4212
>   ARM: dts: exynos3250: Add Mobile Storage Host Card
> 
> Tomasz Figa (11):
>   pinctrl: exynos: Add driver data for Exynos3250
>   clk: samsung: exynos3250: Add clocks using common clock framework
>   ARM: dts: exynos3250: Add new exynos3250.dtsi file
>   ARM: dts: exynos3250: Add GIC dt node for Exynos3250
>   ARM: dts: exynos3250: Add pin control device tree data
>   ARM: dts: exynos3250: Add device tree nodes for clock controllers
>   ARM: dts: exynos3250: Move definitions of external clocks to SoC dtsi
>   ARM: dts: exynos3250: Add amba and pdma dt node
>   ARM: dts: exynos3250: Add spi dt node to support spi bus
>   ARM: dts: exynos3250: Add pwm dt node to support PWM Timer
>   ARM: dts: exynos3250: Add RTC dt node
> 
>  arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 ++++++++++++++++++
>  arch/arm/boot/dts/exynos3250.dtsi         | 410 ++++++++++++++++
>  arch/arm/mach-exynos/Kconfig              |  22 +
>  arch/arm/mach-exynos/exynos.c             |  18 +
>  arch/arm/mach-exynos/firmware.c           |  17 +-
>  arch/arm/mach-exynos/hotplug.c            |  13 +-
>  arch/arm/mach-exynos/include/mach/map.h   |   2 +
>  arch/arm/plat-samsung/include/plat/cpu.h  |  10 +
>  drivers/clk/samsung/Makefile              |   1 +
>  drivers/clk/samsung/clk-exynos3250.c      | 785 ++++++++++++++++++++++++++++++
>  drivers/irqchip/irq-gic.c                 |   1 +
>  drivers/pinctrl/pinctrl-exynos.c          |  67 +++
>  drivers/pinctrl/pinctrl-samsung.c         |   2 +
>  drivers/pinctrl/pinctrl-samsung.h         |   1 +
>  include/dt-bindings/clock/exynos3250.h    | 256 ++++++++++
>  15 files changed, 2077 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>  create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>  create mode 100644 drivers/clk/samsung/clk-exynos3250.c
>  create mode 100644 include/dt-bindings/clock/exynos3250.h
> 

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:23 Chanwoo Choi wrote:
> +        * while Exynos5 is A15/Exynos7 is A7; check the CPU part
> 

Exynos7 -> Exynos3 ?

	Arnd

[PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:23 Chanwoo Choi wrote:
> +        * while Exynos5 is A15/Exynos7 is A7; check the CPU part
> 

Exynos7 -> Exynos3 ?

	Arnd

Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:18 Chanwoo Choi wrote:
> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
> dual cores and has a target speed of 1.0GHz.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
>  arch/arm/mach-exynos/exynos.c            |  1 +
>  arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
>  3 files changed, 33 insertions(+)
> 
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index fc8bf18..6da8a68 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -11,6 +11,17 @@ if ARCH_EXYNOS
>  
>  menu "SAMSUNG EXYNOS SoCs Support"
>  
> +config ARCH_EXYNOS3
> +	bool "SAMSUNG EXYNOS3"
> +	select ARM_AMBA
> +	select CLKSRC_OF
> +	select HAVE_ARM_SCU if SMP
> +	select HAVE_SMP
> +	select PINCTRL
> +	select PM_GENERIC_DOMAINS if PM_RUNTIME
> +	help
> +	  Samsung EXYNOS3 SoCs based systems
> +

Isn't S5PV210 also called an Exynos3 these days? Are we going to get
any conflicts here when merging that code into Exynos as Tomasz has
suggested in the past?

	Arnd

Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:18 Chanwoo Choi wrote:
> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
> dual cores and has a target speed of 1.0GHz.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
>  arch/arm/mach-exynos/exynos.c            |  1 +
>  arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
>  3 files changed, 33 insertions(+)
> 
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index fc8bf18..6da8a68 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -11,6 +11,17 @@ if ARCH_EXYNOS
>  
>  menu "SAMSUNG EXYNOS SoCs Support"
>  
> +config ARCH_EXYNOS3
> +	bool "SAMSUNG EXYNOS3"
> +	select ARM_AMBA
> +	select CLKSRC_OF
> +	select HAVE_ARM_SCU if SMP
> +	select HAVE_SMP
> +	select PINCTRL
> +	select PM_GENERIC_DOMAINS if PM_RUNTIME
> +	help
> +	  Samsung EXYNOS3 SoCs based systems
> +

Isn't S5PV210 also called an Exynos3 these days? Are we going to get
any conflicts here when merging that code into Exynos as Tomasz has
suggested in the past?

	Arnd

[PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:18 Chanwoo Choi wrote:
> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
> dual cores and has a target speed of 1.0GHz.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
>  arch/arm/mach-exynos/exynos.c            |  1 +
>  arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
>  3 files changed, 33 insertions(+)
> 
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index fc8bf18..6da8a68 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -11,6 +11,17 @@ if ARCH_EXYNOS
>  
>  menu "SAMSUNG EXYNOS SoCs Support"
>  
> +config ARCH_EXYNOS3
> +	bool "SAMSUNG EXYNOS3"
> +	select ARM_AMBA
> +	select CLKSRC_OF
> +	select HAVE_ARM_SCU if SMP
> +	select HAVE_SMP
> +	select PINCTRL
> +	select PM_GENERIC_DOMAINS if PM_RUNTIME
> +	help
> +	  Samsung EXYNOS3 SoCs based systems
> +

Isn't S5PV210 also called an Exynos3 these days? Are we going to get
any conflicts here when merging that code into Exynos as Tomasz has
suggested in the past?

	Arnd

Re: [PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:19 Chanwoo Choi wrote:
> 
> The non-secure SYSRAM is used for secondary CPU bring-up. This patch add
> IO mapping for non-scure SYSRAM.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

I really don't want to see any further static mappings here. We had the
same discussion for the previous Exynos chip that was submitted, so please
describe the SYSRAM in DT, and start thinking about the other static mappings
that can be removed.

	Arnd

Re: [PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:19 Chanwoo Choi wrote:
> 
> The non-secure SYSRAM is used for secondary CPU bring-up. This patch add
> IO mapping for non-scure SYSRAM.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

I really don't want to see any further static mappings here. We had the
same discussion for the previous Exynos chip that was submitted, so please
describe the SYSRAM in DT, and start thinking about the other static mappings
that can be removed.

	Arnd

[PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:19 Chanwoo Choi wrote:
> 
> The non-secure SYSRAM is used for secondary CPU bring-up. This patch add
> IO mapping for non-scure SYSRAM.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

I really don't want to see any further static mappings here. We had the
same discussion for the previous Exynos chip that was submitted, so please
describe the SYSRAM in DT, and start thinking about the other static mappings
that can be removed.

	Arnd

Re: [PATCH 03/27] ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:20 Chanwoo Choi wrote:
> This patch add memory mapping for PMU (Power Management Unit) which is used
> for power control of Exynos3250.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Same thing as for the SRAM here, can you work on making this a proper
driver instead?

	Arnd

Re: [PATCH 03/27] ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:20 Chanwoo Choi wrote:
> This patch add memory mapping for PMU (Power Management Unit) which is used
> for power control of Exynos3250.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Same thing as for the SRAM here, can you work on making this a proper
driver instead?

	Arnd

[PATCH 03/27] ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

[Arnd Bergmann]

On Thursday 10 April 2014 18:28:20 Chanwoo Choi wrote:
> This patch add memory mapping for PMU (Power Management Unit) which is used
> for power control of Exynos3250.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Same thing as for the SRAM here, can you work on making this a proper
driver instead?

	Arnd

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Marc Zyngier]

On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch decide proper lowpower mode of either a15 or a9 according to own ID
> from Main ID register.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
> index 5eead53..36d3db6 100644
> --- a/arch/arm/mach-exynos/hotplug.c
> +++ b/arch/arm/mach-exynos/hotplug.c
> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>  	int primary_part = 0;
>  
>  	/*
> -	 * we're ready for shutdown now, so do it.
> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>  	 * number by reading the Main ID register and then perform the
>  	 * appropriate sequence for entering low power.
>  	 */
>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");

While you're touching that code, how about using:

      primary_part = read_cpuid(CPUID_ID);

> -	if ((primary_part & 0xfff0) == 0xc0f0)
> +
> +	/*
> +	 * Main ID register of Cortex series
> +	 * - Cortex-a7  : 0x410F_C07x
> +	 * - Cortex-a15 : 0x410F_C0Fx
> +	 */
> +	primary_part = primary_part & 0xfff0;
> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)

ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7

>  		cpu_enter_lowpower_a15();
>  	else
>  		cpu_enter_lowpower_a9();

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Marc Zyngier]

On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch decide proper lowpower mode of either a15 or a9 according to own ID
> from Main ID register.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
> index 5eead53..36d3db6 100644
> --- a/arch/arm/mach-exynos/hotplug.c
> +++ b/arch/arm/mach-exynos/hotplug.c
> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>  	int primary_part = 0;
>  
>  	/*
> -	 * we're ready for shutdown now, so do it.
> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>  	 * number by reading the Main ID register and then perform the
>  	 * appropriate sequence for entering low power.
>  	 */
>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");

While you're touching that code, how about using:

      primary_part = read_cpuid(CPUID_ID);

> -	if ((primary_part & 0xfff0) == 0xc0f0)
> +
> +	/*
> +	 * Main ID register of Cortex series
> +	 * - Cortex-a7  : 0x410F_C07x
> +	 * - Cortex-a15 : 0x410F_C0Fx
> +	 */
> +	primary_part = primary_part & 0xfff0;
> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)

ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7

>  		cpu_enter_lowpower_a15();
>  	else
>  		cpu_enter_lowpower_a9();

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.

[PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Marc Zyngier]

On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch decide proper lowpower mode of either a15 or a9 according to own ID
> from Main ID register.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
> index 5eead53..36d3db6 100644
> --- a/arch/arm/mach-exynos/hotplug.c
> +++ b/arch/arm/mach-exynos/hotplug.c
> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>  	int primary_part = 0;
>  
>  	/*
> -	 * we're ready for shutdown now, so do it.
> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>  	 * number by reading the Main ID register and then perform the
>  	 * appropriate sequence for entering low power.
>  	 */
>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");

While you're touching that code, how about using:

      primary_part = read_cpuid(CPUID_ID);

> -	if ((primary_part & 0xfff0) == 0xc0f0)
> +
> +	/*
> +	 * Main ID register of Cortex series
> +	 * - Cortex-a7  : 0x410F_C07x
> +	 * - Cortex-a15 : 0x410F_C0Fx
> +	 */
> +	primary_part = primary_part & 0xfff0;
> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)

ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7

>  		cpu_enter_lowpower_a15();
>  	else
>  		cpu_enter_lowpower_a9();

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.

RE: [PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250

[Chanho Park]

Hi Arnd,

> -----Original Message-----
> From: linux-arm-kernel [mailto:linux-arm-kernel-
> bounces@lists.infradead.org] On Behalf Of Arnd Bergmann
> Sent: Thursday, April 10, 2014 6:45 PM
> To: linux-arm-kernel@lists.infradead.org
> Cc: kgene.kim@samsung.com; t.figa@samsung.com; hyunhee.kim@samsung.com;
> sw0312.kim@samsung.com; linux-kernel@vger.kernel.org;
> yj44.cho@samsung.com; inki.dae@samsung.com; Chanwoo Choi;
> kyungmin.park@samsung.com; linux-samsung-soc@vger.kernel.org
> Subject: Re: [PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure
> SYSRAM of Exynos3250
> 
> On Thursday 10 April 2014 18:28:19 Chanwoo Choi wrote:
> >
> > The non-secure SYSRAM is used for secondary CPU bring-up. This patch
> add
> > IO mapping for non-scure SYSRAM.
> >
> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> 
> I really don't want to see any further static mappings here. We had the
> same discussion for the previous Exynos chip that was submitted, so
> please
> describe the SYSRAM in DT, and start thinking about the other static
> mappings
> that can be removed.

Sachin already submitted the DT support[1] for SYSRAM area.

[1] : http://www.spinics.net/lists/linux-samsung-soc/msg27647.html

> 
> 	Arnd
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250

[Chanho Park]

Hi Arnd,

> -----Original Message-----
> From: linux-arm-kernel [mailto:linux-arm-kernel-
> bounces at lists.infradead.org] On Behalf Of Arnd Bergmann
> Sent: Thursday, April 10, 2014 6:45 PM
> To: linux-arm-kernel at lists.infradead.org
> Cc: kgene.kim at samsung.com; t.figa at samsung.com; hyunhee.kim at samsung.com;
> sw0312.kim at samsung.com; linux-kernel at vger.kernel.org;
> yj44.cho at samsung.com; inki.dae at samsung.com; Chanwoo Choi;
> kyungmin.park at samsung.com; linux-samsung-soc at vger.kernel.org
> Subject: Re: [PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure
> SYSRAM of Exynos3250
> 
> On Thursday 10 April 2014 18:28:19 Chanwoo Choi wrote:
> >
> > The non-secure SYSRAM is used for secondary CPU bring-up. This patch
> add
> > IO mapping for non-scure SYSRAM.
> >
> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> 
> I really don't want to see any further static mappings here. We had the
> same discussion for the previous Exynos chip that was submitted, so
> please
> describe the SYSRAM in DT, and start thinking about the other static
> mappings
> that can be removed.

Sachin already submitted the DT support[1] for SYSRAM area.

[1] : http://www.spinics.net/lists/linux-samsung-soc/msg27647.html

> 
> 	Arnd
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch declare coretex-a7's irqchip to initialze gic from dt
> with "arm,cortex-a7-gic" data.
>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  drivers/irqchip/irq-gic.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 4300b66..8e906e4 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>  }
>  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);

Frankly, this patch adds no value. Are we going to add
"arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
"arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...

Instead, how about defining a generic "arm,gic" property, and mandate
that new DT files are using that? We can always use a more precise
compatible for quirks.

Mark, what do you think? I think this has been discussed in the past
already.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch declare coretex-a7's irqchip to initialze gic from dt
> with "arm,cortex-a7-gic" data.
>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  drivers/irqchip/irq-gic.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 4300b66..8e906e4 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>  }
>  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);

Frankly, this patch adds no value. Are we going to add
"arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
"arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...

Instead, how about defining a generic "arm,gic" property, and mandate
that new DT files are using that? We can always use a more precise
compatible for quirks.

Mark, what do you think? I think this has been discussed in the past
already.

	M.
-- 
Jazz is not dead. It just smells funny.

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch declare coretex-a7's irqchip to initialze gic from dt
> with "arm,cortex-a7-gic" data.
>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  drivers/irqchip/irq-gic.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 4300b66..8e906e4 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>  }
>  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);

Frankly, this patch adds no value. Are we going to add
"arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
"arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...

Instead, how about defining a generic "arm,gic" property, and mandate
that new DT files are using that? We can always use a more precise
compatible for quirks.

Mark, what do you think? I think this has been discussed in the past
already.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[armdev]

On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:

> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch declare coretex-a7's irqchip to initialze gic from dt
>> with "arm,cortex-a7-gic" data.
>> 
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>> drivers/irqchip/irq-gic.c | 1 +
>> 1 file changed, 1 insertion(+)
>> 
>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>> index 4300b66..8e906e4 100644
>> --- a/drivers/irqchip/irq-gic.c
>> +++ b/drivers/irqchip/irq-gic.c
>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>> }
>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
> 
> Frankly, this patch adds no value. Are we going to add
> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
> 
> Instead, how about defining a generic "arm,gic" property, and mandate
> that new DT files are using that? We can always use a more precise
> compatible for quirks.
> 

How about keeping it simple and tied to arm gic versions
arm,gicv1, arm,gicv2, arm,gicv2ve

> Mark, what do you think? I think this has been discussed in the past
> already.
> 
> 	M.
> -- 
> Jazz is not dead. It just smells funny.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[armdev]

On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:

> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch declare coretex-a7's irqchip to initialze gic from dt
>> with "arm,cortex-a7-gic" data.
>> 
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>> drivers/irqchip/irq-gic.c | 1 +
>> 1 file changed, 1 insertion(+)
>> 
>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>> index 4300b66..8e906e4 100644
>> --- a/drivers/irqchip/irq-gic.c
>> +++ b/drivers/irqchip/irq-gic.c
>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>> }
>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
> 
> Frankly, this patch adds no value. Are we going to add
> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
> 
> Instead, how about defining a generic "arm,gic" property, and mandate
> that new DT files are using that? We can always use a more precise
> compatible for quirks.
> 

How about keeping it simple and tied to arm gic versions
arm,gicv1, arm,gicv2, arm,gicv2ve

> Mark, what do you think? I think this has been discussed in the past
> already.
> 
> 	M.
> -- 
> Jazz is not dead. It just smells funny.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[armdev]

On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:

> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch declare coretex-a7's irqchip to initialze gic from dt
>> with "arm,cortex-a7-gic" data.
>> 
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>> drivers/irqchip/irq-gic.c | 1 +
>> 1 file changed, 1 insertion(+)
>> 
>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>> index 4300b66..8e906e4 100644
>> --- a/drivers/irqchip/irq-gic.c
>> +++ b/drivers/irqchip/irq-gic.c
>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>> }
>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
> 
> Frankly, this patch adds no value. Are we going to add
> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
> 
> Instead, how about defining a generic "arm,gic" property, and mandate
> that new DT files are using that? We can always use a more precise
> compatible for quirks.
> 

How about keeping it simple and tied to arm gic versions
arm,gicv1, arm,gicv2, arm,gicv2ve

> Mark, what do you think? I think this has been discussed in the past
> already.
> 
> 	M.
> -- 
> Jazz is not dead. It just smells funny.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>
>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>> with "arm,cortex-a7-gic" data.
>>> 
>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>> drivers/irqchip/irq-gic.c | 1 +
>>> 1 file changed, 1 insertion(+)
>>> 
>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>> index 4300b66..8e906e4 100644
>>> --- a/drivers/irqchip/irq-gic.c
>>> +++ b/drivers/irqchip/irq-gic.c
>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>> }
>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>> 
>> Frankly, this patch adds no value. Are we going to add
>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>> 
>> Instead, how about defining a generic "arm,gic" property, and mandate
>> that new DT files are using that? We can always use a more precise
>> compatible for quirks.
>> 
>
> How about keeping it simple and tied to arm gic versions
> arm,gicv1, arm,gicv2, arm,gicv2ve

That's a variation on the same theme. As for GICv2, we don't need to
distinguish between having the Virtualization Extentions, the binding
already allows you to tell one from the other.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>
>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>> with "arm,cortex-a7-gic" data.
>>> 
>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>> drivers/irqchip/irq-gic.c | 1 +
>>> 1 file changed, 1 insertion(+)
>>> 
>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>> index 4300b66..8e906e4 100644
>>> --- a/drivers/irqchip/irq-gic.c
>>> +++ b/drivers/irqchip/irq-gic.c
>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>> }
>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>> 
>> Frankly, this patch adds no value. Are we going to add
>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>> 
>> Instead, how about defining a generic "arm,gic" property, and mandate
>> that new DT files are using that? We can always use a more precise
>> compatible for quirks.
>> 
>
> How about keeping it simple and tied to arm gic versions
> arm,gicv1, arm,gicv2, arm,gicv2ve

That's a variation on the same theme. As for GICv2, we don't need to
distinguish between having the Virtualization Extentions, the binding
already allows you to tell one from the other.

	M.
-- 
Jazz is not dead. It just smells funny.

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>
>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>> with "arm,cortex-a7-gic" data.
>>> 
>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>> drivers/irqchip/irq-gic.c | 1 +
>>> 1 file changed, 1 insertion(+)
>>> 
>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>> index 4300b66..8e906e4 100644
>>> --- a/drivers/irqchip/irq-gic.c
>>> +++ b/drivers/irqchip/irq-gic.c
>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>> }
>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>> 
>> Frankly, this patch adds no value. Are we going to add
>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>> 
>> Instead, how about defining a generic "arm,gic" property, and mandate
>> that new DT files are using that? We can always use a more precise
>> compatible for quirks.
>> 
>
> How about keeping it simple and tied to arm gic versions
> arm,gicv1, arm,gicv2, arm,gicv2ve

That's a variation on the same theme. As for GICv2, we don't need to
distinguish between having the Virtualization Extentions, the binding
already allows you to tell one from the other.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[armdev]

On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:

> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> 
>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>> with "arm,cortex-a7-gic" data.
>>>> 
>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>> ---
>>>> drivers/irqchip/irq-gic.c | 1 +
>>>> 1 file changed, 1 insertion(+)
>>>> 
>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>> index 4300b66..8e906e4 100644
>>>> --- a/drivers/irqchip/irq-gic.c
>>>> +++ b/drivers/irqchip/irq-gic.c
>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>> }
>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>> 
>>> Frankly, this patch adds no value. Are we going to add
>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>> 
>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>> that new DT files are using that? We can always use a more precise
>>> compatible for quirks.
>>> 
>> 
>> How about keeping it simple and tied to arm gic versions
>> arm,gicv1, arm,gicv2, arm,gicv2ve
> 
> That's a variation on the same theme. As for GICv2, we don't need to
> distinguish between having the Virtualization Extentions, the binding
> already allows you to tell one from the other.
> 
So if there be just 2 types of gic, it would be simple.
gicv1 - 2 address sets (gicc and gicd)
gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?

> 	M.
> -- 
> Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[armdev]

On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:

> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> 
>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>> with "arm,cortex-a7-gic" data.
>>>> 
>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>> ---
>>>> drivers/irqchip/irq-gic.c | 1 +
>>>> 1 file changed, 1 insertion(+)
>>>> 
>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>> index 4300b66..8e906e4 100644
>>>> --- a/drivers/irqchip/irq-gic.c
>>>> +++ b/drivers/irqchip/irq-gic.c
>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>> }
>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>> 
>>> Frankly, this patch adds no value. Are we going to add
>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>> 
>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>> that new DT files are using that? We can always use a more precise
>>> compatible for quirks.
>>> 
>> 
>> How about keeping it simple and tied to arm gic versions
>> arm,gicv1, arm,gicv2, arm,gicv2ve
> 
> That's a variation on the same theme. As for GICv2, we don't need to
> distinguish between having the Virtualization Extentions, the binding
> already allows you to tell one from the other.
> 
So if there be just 2 types of gic, it would be simple.
gicv1 - 2 address sets (gicc and gicd)
gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?

> 	M.
> -- 
> Jazz is not dead. It just smells funny.

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[armdev]

On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:

> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> 
>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>> with "arm,cortex-a7-gic" data.
>>>> 
>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>> ---
>>>> drivers/irqchip/irq-gic.c | 1 +
>>>> 1 file changed, 1 insertion(+)
>>>> 
>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>> index 4300b66..8e906e4 100644
>>>> --- a/drivers/irqchip/irq-gic.c
>>>> +++ b/drivers/irqchip/irq-gic.c
>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>> }
>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>> 
>>> Frankly, this patch adds no value. Are we going to add
>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>> 
>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>> that new DT files are using that? We can always use a more precise
>>> compatible for quirks.
>>> 
>> 
>> How about keeping it simple and tied to arm gic versions
>> arm,gicv1, arm,gicv2, arm,gicv2ve
> 
> That's a variation on the same theme. As for GICv2, we don't need to
> distinguish between having the Virtualization Extentions, the binding
> already allows you to tell one from the other.
> 
So if there be just 2 types of gic, it would be simple.
gicv1 - 2 address sets (gicc and gicd)
gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?

> 	M.
> -- 
> Jazz is not dead. It just smells funny.

RE: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Chanho Park]

Hi,

> -----Original Message-----
> From: linux-arm-kernel [mailto:linux-arm-kernel-
> bounces@lists.infradead.org] On Behalf Of Marc Zyngier
> Sent: Thursday, April 10, 2014 7:05 PM
> To: Chanwoo Choi
> Cc: mark.rutland@arm.com; linux-samsung-soc@vger.kernel.org;
> t.figa@samsung.com; hyunhee.kim@samsung.com; sw0312.kim@samsung.com;
> linux-kernel@vger.kernel.org; yj44.cho@samsung.com; inki.dae@samsung.com;
> kyungmin.park@samsung.com; kgene.kim@samsung.com; Thomas Gleixner;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to
> initialize gic from dt
> 
> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi
> <cw00.choi@samsung.com> wrote:
> > This patch declare coretex-a7's irqchip to initialze gic from dt
> > with "arm,cortex-a7-gic" data.
> >
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >  drivers/irqchip/irq-gic.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > index 4300b66..8e906e4 100644
> > --- a/drivers/irqchip/irq-gic.c
> > +++ b/drivers/irqchip/irq-gic.c
> > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct
> device_node *parent)
> >  }
> >  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
> >  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
> > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
> 
> Frankly, this patch adds no value. Are we going to add
> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
> 
> Instead, how about defining a generic "arm,gic" property, and mandate
> that new DT files are using that? We can always use a more precise
> compatible for quirks.

I prefer it would be arm,gicv2 instead arm-gic.
In case of GICv3 of arm64, it can be arm,gicv3.

Best Regards,
Chanho Park

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Chanho Park]

Hi,

> -----Original Message-----
> From: linux-arm-kernel [mailto:linux-arm-kernel-
> bounces at lists.infradead.org] On Behalf Of Marc Zyngier
> Sent: Thursday, April 10, 2014 7:05 PM
> To: Chanwoo Choi
> Cc: mark.rutland at arm.com; linux-samsung-soc at vger.kernel.org;
> t.figa at samsung.com; hyunhee.kim at samsung.com; sw0312.kim at samsung.com;
> linux-kernel at vger.kernel.org; yj44.cho at samsung.com; inki.dae at samsung.com;
> kyungmin.park at samsung.com; kgene.kim at samsung.com; Thomas Gleixner;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to
> initialize gic from dt
> 
> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi
> <cw00.choi@samsung.com> wrote:
> > This patch declare coretex-a7's irqchip to initialze gic from dt
> > with "arm,cortex-a7-gic" data.
> >
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >  drivers/irqchip/irq-gic.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > index 4300b66..8e906e4 100644
> > --- a/drivers/irqchip/irq-gic.c
> > +++ b/drivers/irqchip/irq-gic.c
> > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct
> device_node *parent)
> >  }
> >  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
> >  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
> > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
> 
> Frankly, this patch adds no value. Are we going to add
> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
> 
> Instead, how about defining a generic "arm,gic" property, and mandate
> that new DT files are using that? We can always use a more precise
> compatible for quirks.

I prefer it would be arm,gicv2 instead arm-gic.
In case of GICv3 of arm64, it can be arm,gicv3.

Best Regards,
Chanho Park

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

On 04/10/2014 06:40 PM, Arnd Bergmann wrote:
> On Thursday 10 April 2014 18:28:23 Chanwoo Choi wrote:
>> +        * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>
> 
> Exynos7 -> Exynos3 ?
> 

You're right. I'll fix it.

Best Regards,
Chanwoo Choi

[PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

On 04/10/2014 06:40 PM, Arnd Bergmann wrote:
> On Thursday 10 April 2014 18:28:23 Chanwoo Choi wrote:
>> +        * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>
> 
> Exynos7 -> Exynos3 ?
> 

You're right. I'll fix it.

Best Regards,
Chanwoo Choi

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:30:41 am BST, armdev <armdev.ftm@gmail.com> wrote:
> On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>
>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>> 
>>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>>> with "arm,cortex-a7-gic" data.
>>>>> 
>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>> ---
>>>>> drivers/irqchip/irq-gic.c | 1 +
>>>>> 1 file changed, 1 insertion(+)
>>>>> 
>>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>>> index 4300b66..8e906e4 100644
>>>>> --- a/drivers/irqchip/irq-gic.c
>>>>> +++ b/drivers/irqchip/irq-gic.c
>>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>>> }
>>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>>> 
>>>> Frankly, this patch adds no value. Are we going to add
>>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>>> 
>>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>>> that new DT files are using that? We can always use a more precise
>>>> compatible for quirks.
>>>> 
>>> 
>>> How about keeping it simple and tied to arm gic versions
>>> arm,gicv1, arm,gicv2, arm,gicv2ve
>> 
>> That's a variation on the same theme. As for GICv2, we don't need to
>> distinguish between having the Virtualization Extentions, the binding
>> already allows you to tell one from the other.
>> 
> So if there be just 2 types of gic, it would be simple.

Not exactly. We just happen to support two revisions of the GIC
architecture with the same binding. GICv3 has an entierely separate
binding.

> gicv1 - 2 address sets (gicc and gicd)

Yes.

> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?

No.

The presence of the GICV, GICH and maintenance interrupt are indicative
of the support for the Virtualization Extentions. GICv2 itself can
perfectly be built without it.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:30:41 am BST, armdev <armdev.ftm@gmail.com> wrote:
> On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>
>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>> 
>>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>>> with "arm,cortex-a7-gic" data.
>>>>> 
>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>> ---
>>>>> drivers/irqchip/irq-gic.c | 1 +
>>>>> 1 file changed, 1 insertion(+)
>>>>> 
>>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>>> index 4300b66..8e906e4 100644
>>>>> --- a/drivers/irqchip/irq-gic.c
>>>>> +++ b/drivers/irqchip/irq-gic.c
>>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>>> }
>>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>>> 
>>>> Frankly, this patch adds no value. Are we going to add
>>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>>> 
>>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>>> that new DT files are using that? We can always use a more precise
>>>> compatible for quirks.
>>>> 
>>> 
>>> How about keeping it simple and tied to arm gic versions
>>> arm,gicv1, arm,gicv2, arm,gicv2ve
>> 
>> That's a variation on the same theme. As for GICv2, we don't need to
>> distinguish between having the Virtualization Extentions, the binding
>> already allows you to tell one from the other.
>> 
> So if there be just 2 types of gic, it would be simple.

Not exactly. We just happen to support two revisions of the GIC
architecture with the same binding. GICv3 has an entierely separate
binding.

> gicv1 - 2 address sets (gicc and gicd)

Yes.

> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?

No.

The presence of the GICV, GICH and maintenance interrupt are indicative
of the support for the Virtualization Extentions. GICv2 itself can
perfectly be built without it.

	M.
-- 
Jazz is not dead. It just smells funny.

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:30:41 am BST, armdev <armdev.ftm@gmail.com> wrote:
> On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>
>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>> 
>>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>>> with "arm,cortex-a7-gic" data.
>>>>> 
>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>> ---
>>>>> drivers/irqchip/irq-gic.c | 1 +
>>>>> 1 file changed, 1 insertion(+)
>>>>> 
>>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>>> index 4300b66..8e906e4 100644
>>>>> --- a/drivers/irqchip/irq-gic.c
>>>>> +++ b/drivers/irqchip/irq-gic.c
>>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>>> }
>>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>>> 
>>>> Frankly, this patch adds no value. Are we going to add
>>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>>> 
>>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>>> that new DT files are using that? We can always use a more precise
>>>> compatible for quirks.
>>>> 
>>> 
>>> How about keeping it simple and tied to arm gic versions
>>> arm,gicv1, arm,gicv2, arm,gicv2ve
>> 
>> That's a variation on the same theme. As for GICv2, we don't need to
>> distinguish between having the Virtualization Extentions, the binding
>> already allows you to tell one from the other.
>> 
> So if there be just 2 types of gic, it would be simple.

Not exactly. We just happen to support two revisions of the GIC
architecture with the same binding. GICv3 has an entierely separate
binding.

> gicv1 - 2 address sets (gicc and gicd)

Yes.

> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?

No.

The presence of the GICV, GICH and maintenance interrupt are indicative
of the support for the Virtualization Extentions. GICv2 itself can
perfectly be built without it.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[armdev]

On 10-Apr-2014, at 4:11 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:

> On Thu, Apr 10 2014 at 11:30:41 am BST, armdev <armdev.ftm@gmail.com> wrote:
>> On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> 
>>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>>> 
>>>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>>>> with "arm,cortex-a7-gic" data.
>>>>>> 
>>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>>> ---
>>>>>> drivers/irqchip/irq-gic.c | 1 +
>>>>>> 1 file changed, 1 insertion(+)
>>>>>> 
>>>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>>>> index 4300b66..8e906e4 100644
>>>>>> --- a/drivers/irqchip/irq-gic.c
>>>>>> +++ b/drivers/irqchip/irq-gic.c
>>>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>>>> }
>>>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>>>> 
>>>>> Frankly, this patch adds no value. Are we going to add
>>>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>>>> 
>>>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>>>> that new DT files are using that? We can always use a more precise
>>>>> compatible for quirks.
>>>>> 
>>>> 
>>>> How about keeping it simple and tied to arm gic versions
>>>> arm,gicv1, arm,gicv2, arm,gicv2ve
>>> 
>>> That's a variation on the same theme. As for GICv2, we don't need to
>>> distinguish between having the Virtualization Extentions, the binding
>>> already allows you to tell one from the other.
>>> 
>> So if there be just 2 types of gic, it would be simple.
> 
> Not exactly. We just happen to support two revisions of the GIC
> architecture with the same binding. GICv3 has an entierely separate
> binding.
> 
>> gicv1 - 2 address sets (gicc and gicd)
> 
> Yes.
> 
>> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?
> 
> No.
> 
> The presence of the GICV, GICH and maintenance interrupt are indicative
> of the support for the Virtualization Extentions. GICv2 itself can
> perfectly be built without it.

then does gicv2-ve makes sense ?
> 
> 	M.
> -- 
> Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[armdev]

On 10-Apr-2014, at 4:11 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:

> On Thu, Apr 10 2014 at 11:30:41 am BST, armdev <armdev.ftm@gmail.com> wrote:
>> On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> 
>>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>>> 
>>>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>>>> with "arm,cortex-a7-gic" data.
>>>>>> 
>>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>>> ---
>>>>>> drivers/irqchip/irq-gic.c | 1 +
>>>>>> 1 file changed, 1 insertion(+)
>>>>>> 
>>>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>>>> index 4300b66..8e906e4 100644
>>>>>> --- a/drivers/irqchip/irq-gic.c
>>>>>> +++ b/drivers/irqchip/irq-gic.c
>>>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>>>> }
>>>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>>>> 
>>>>> Frankly, this patch adds no value. Are we going to add
>>>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>>>> 
>>>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>>>> that new DT files are using that? We can always use a more precise
>>>>> compatible for quirks.
>>>>> 
>>>> 
>>>> How about keeping it simple and tied to arm gic versions
>>>> arm,gicv1, arm,gicv2, arm,gicv2ve
>>> 
>>> That's a variation on the same theme. As for GICv2, we don't need to
>>> distinguish between having the Virtualization Extentions, the binding
>>> already allows you to tell one from the other.
>>> 
>> So if there be just 2 types of gic, it would be simple.
> 
> Not exactly. We just happen to support two revisions of the GIC
> architecture with the same binding. GICv3 has an entierely separate
> binding.
> 
>> gicv1 - 2 address sets (gicc and gicd)
> 
> Yes.
> 
>> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?
> 
> No.
> 
> The presence of the GICV, GICH and maintenance interrupt are indicative
> of the support for the Virtualization Extentions. GICv2 itself can
> perfectly be built without it.

then does gicv2-ve makes sense ?
> 
> 	M.
> -- 
> Jazz is not dead. It just smells funny.

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[armdev]

On 10-Apr-2014, at 4:11 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:

> On Thu, Apr 10 2014 at 11:30:41 am BST, armdev <armdev.ftm@gmail.com> wrote:
>> On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> 
>>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>>> 
>>>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>>>> with "arm,cortex-a7-gic" data.
>>>>>> 
>>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>>> ---
>>>>>> drivers/irqchip/irq-gic.c | 1 +
>>>>>> 1 file changed, 1 insertion(+)
>>>>>> 
>>>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>>>> index 4300b66..8e906e4 100644
>>>>>> --- a/drivers/irqchip/irq-gic.c
>>>>>> +++ b/drivers/irqchip/irq-gic.c
>>>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>>>> }
>>>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>>>> 
>>>>> Frankly, this patch adds no value. Are we going to add
>>>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>>>> 
>>>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>>>> that new DT files are using that? We can always use a more precise
>>>>> compatible for quirks.
>>>>> 
>>>> 
>>>> How about keeping it simple and tied to arm gic versions
>>>> arm,gicv1, arm,gicv2, arm,gicv2ve
>>> 
>>> That's a variation on the same theme. As for GICv2, we don't need to
>>> distinguish between having the Virtualization Extentions, the binding
>>> already allows you to tell one from the other.
>>> 
>> So if there be just 2 types of gic, it would be simple.
> 
> Not exactly. We just happen to support two revisions of the GIC
> architecture with the same binding. GICv3 has an entierely separate
> binding.
> 
>> gicv1 - 2 address sets (gicc and gicd)
> 
> Yes.
> 
>> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?
> 
> No.
> 
> The presence of the GICV, GICH and maintenance interrupt are indicative
> of the support for the Virtualization Extentions. GICv2 itself can
> perfectly be built without it.

then does gicv2-ve makes sense ?
> 
> 	M.
> -- 
> Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:37:12 am BST, Chanho Park <chanho61.park@samsung.com> wrote:
> Hi,
>
>> -----Original Message-----
>> From: linux-arm-kernel [mailto:linux-arm-kernel-
>> bounces@lists.infradead.org] On Behalf Of Marc Zyngier
>> Sent: Thursday, April 10, 2014 7:05 PM
>> To: Chanwoo Choi
>> Cc: mark.rutland@arm.com; linux-samsung-soc@vger.kernel.org;
>> t.figa@samsung.com; hyunhee.kim@samsung.com; sw0312.kim@samsung.com;
>> linux-kernel@vger.kernel.org; yj44.cho@samsung.com; inki.dae@samsung.com;
>> kyungmin.park@samsung.com; kgene.kim@samsung.com; Thomas Gleixner;
>> linux-arm-kernel@lists.infradead.org
>> Subject: Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to
>> initialize gic from dt
>> 
>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi
>> <cw00.choi@samsung.com> wrote:
>> > This patch declare coretex-a7's irqchip to initialze gic from dt
>> > with "arm,cortex-a7-gic" data.
>> >
>> > Cc: Thomas Gleixner <tglx@linutronix.de>
>> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> > ---
>> >  drivers/irqchip/irq-gic.c | 1 +
>> >  1 file changed, 1 insertion(+)
>> >
>> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>> > index 4300b66..8e906e4 100644
>> > --- a/drivers/irqchip/irq-gic.c
>> > +++ b/drivers/irqchip/irq-gic.c
>> > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct
>> device_node *parent)
>> >  }
>> >  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>> >  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>> > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>> >  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>> >  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>> 
>> Frankly, this patch adds no value. Are we going to add
>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>> 
>> Instead, how about defining a generic "arm,gic" property, and mandate
>> that new DT files are using that? We can always use a more precise
>> compatible for quirks.
>
> I prefer it would be arm,gicv2 instead arm-gic.

If you prefer, fine by me. Consider spelling it "arm,gic-v2", which
seems to be the current convention for version numbers.

> In case of GICv3 of arm64, it can be arm,gicv3.

GICv3 and arm64 are independent of each other, and the binding has
already been specified as "arm,gic-v3".

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:37:12 am BST, Chanho Park <chanho61.park@samsung.com> wrote:
> Hi,
>
>> -----Original Message-----
>> From: linux-arm-kernel [mailto:linux-arm-kernel-
>> bounces@lists.infradead.org] On Behalf Of Marc Zyngier
>> Sent: Thursday, April 10, 2014 7:05 PM
>> To: Chanwoo Choi
>> Cc: mark.rutland@arm.com; linux-samsung-soc@vger.kernel.org;
>> t.figa@samsung.com; hyunhee.kim@samsung.com; sw0312.kim@samsung.com;
>> linux-kernel@vger.kernel.org; yj44.cho@samsung.com; inki.dae@samsung.com;
>> kyungmin.park@samsung.com; kgene.kim@samsung.com; Thomas Gleixner;
>> linux-arm-kernel@lists.infradead.org
>> Subject: Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to
>> initialize gic from dt
>> 
>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi
>> <cw00.choi@samsung.com> wrote:
>> > This patch declare coretex-a7's irqchip to initialze gic from dt
>> > with "arm,cortex-a7-gic" data.
>> >
>> > Cc: Thomas Gleixner <tglx@linutronix.de>
>> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> > ---
>> >  drivers/irqchip/irq-gic.c | 1 +
>> >  1 file changed, 1 insertion(+)
>> >
>> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>> > index 4300b66..8e906e4 100644
>> > --- a/drivers/irqchip/irq-gic.c
>> > +++ b/drivers/irqchip/irq-gic.c
>> > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct
>> device_node *parent)
>> >  }
>> >  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>> >  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>> > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>> >  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>> >  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>> 
>> Frankly, this patch adds no value. Are we going to add
>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>> 
>> Instead, how about defining a generic "arm,gic" property, and mandate
>> that new DT files are using that? We can always use a more precise
>> compatible for quirks.
>
> I prefer it would be arm,gicv2 instead arm-gic.

If you prefer, fine by me. Consider spelling it "arm,gic-v2", which
seems to be the current convention for version numbers.

> In case of GICv3 of arm64, it can be arm,gicv3.

GICv3 and arm64 are independent of each other, and the binding has
already been specified as "arm,gic-v3".

	M.
-- 
Jazz is not dead. It just smells funny.

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:37:12 am BST, Chanho Park <chanho61.park@samsung.com> wrote:
> Hi,
>
>> -----Original Message-----
>> From: linux-arm-kernel [mailto:linux-arm-kernel-
>> bounces at lists.infradead.org] On Behalf Of Marc Zyngier
>> Sent: Thursday, April 10, 2014 7:05 PM
>> To: Chanwoo Choi
>> Cc: mark.rutland at arm.com; linux-samsung-soc at vger.kernel.org;
>> t.figa at samsung.com; hyunhee.kim at samsung.com; sw0312.kim at samsung.com;
>> linux-kernel at vger.kernel.org; yj44.cho at samsung.com; inki.dae at samsung.com;
>> kyungmin.park at samsung.com; kgene.kim at samsung.com; Thomas Gleixner;
>> linux-arm-kernel at lists.infradead.org
>> Subject: Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to
>> initialize gic from dt
>> 
>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi
>> <cw00.choi@samsung.com> wrote:
>> > This patch declare coretex-a7's irqchip to initialze gic from dt
>> > with "arm,cortex-a7-gic" data.
>> >
>> > Cc: Thomas Gleixner <tglx@linutronix.de>
>> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> > ---
>> >  drivers/irqchip/irq-gic.c | 1 +
>> >  1 file changed, 1 insertion(+)
>> >
>> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>> > index 4300b66..8e906e4 100644
>> > --- a/drivers/irqchip/irq-gic.c
>> > +++ b/drivers/irqchip/irq-gic.c
>> > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct
>> device_node *parent)
>> >  }
>> >  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>> >  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>> > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>> >  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>> >  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>> 
>> Frankly, this patch adds no value. Are we going to add
>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>> 
>> Instead, how about defining a generic "arm,gic" property, and mandate
>> that new DT files are using that? We can always use a more precise
>> compatible for quirks.
>
> I prefer it would be arm,gicv2 instead arm-gic.

If you prefer, fine by me. Consider spelling it "arm,gic-v2", which
seems to be the current convention for version numbers.

> In case of GICv3 of arm64, it can be arm,gicv3.

GICv3 and arm64 are independent of each other, and the binding has
already been specified as "arm,gic-v3".

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:42:56 am BST, armdev <armdev.ftm@gmail.com> wrote:
> On 10-Apr-2014, at 4:11 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>
>> On Thu, Apr 10 2014 at 11:30:41 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>> On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>> 
>>>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>>>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>>>> 
>>>>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>>>>> with "arm,cortex-a7-gic" data.
>>>>>>> 
>>>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>>>> ---
>>>>>>> drivers/irqchip/irq-gic.c | 1 +
>>>>>>> 1 file changed, 1 insertion(+)
>>>>>>> 
>>>>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>>>>> index 4300b66..8e906e4 100644
>>>>>>> --- a/drivers/irqchip/irq-gic.c
>>>>>>> +++ b/drivers/irqchip/irq-gic.c
>>>>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>>>>> }
>>>>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>>>>> 
>>>>>> Frankly, this patch adds no value. Are we going to add
>>>>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>>>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>>>>> 
>>>>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>>>>> that new DT files are using that? We can always use a more precise
>>>>>> compatible for quirks.
>>>>>> 
>>>>> 
>>>>> How about keeping it simple and tied to arm gic versions
>>>>> arm,gicv1, arm,gicv2, arm,gicv2ve
>>>> 
>>>> That's a variation on the same theme. As for GICv2, we don't need to
>>>> distinguish between having the Virtualization Extentions, the binding
>>>> already allows you to tell one from the other.
>>>> 
>>> So if there be just 2 types of gic, it would be simple.
>> 
>> Not exactly. We just happen to support two revisions of the GIC
>> architecture with the same binding. GICv3 has an entierely separate
>> binding.
>> 
>>> gicv1 - 2 address sets (gicc and gicd)
>> 
>> Yes.
>> 
>>> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?
>> 
>> No.
>> 
>> The presence of the GICV, GICH and maintenance interrupt are indicative
>> of the support for the Virtualization Extentions. GICv2 itself can
>> perfectly be built without it.
>
> then does gicv2-ve makes sense ?

Read what I just wrote. You find the GICV region, you have the VE
extensions. You don't find them, they are not present. No need for an
overloaded compatible string, they both conform to the same
*Architecture Spec*.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:42:56 am BST, armdev <armdev.ftm@gmail.com> wrote:
> On 10-Apr-2014, at 4:11 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>
>> On Thu, Apr 10 2014 at 11:30:41 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>> On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>> 
>>>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>>>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>>>> 
>>>>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>>>>> with "arm,cortex-a7-gic" data.
>>>>>>> 
>>>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>>>> ---
>>>>>>> drivers/irqchip/irq-gic.c | 1 +
>>>>>>> 1 file changed, 1 insertion(+)
>>>>>>> 
>>>>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>>>>> index 4300b66..8e906e4 100644
>>>>>>> --- a/drivers/irqchip/irq-gic.c
>>>>>>> +++ b/drivers/irqchip/irq-gic.c
>>>>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>>>>> }
>>>>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>>>>> 
>>>>>> Frankly, this patch adds no value. Are we going to add
>>>>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>>>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>>>>> 
>>>>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>>>>> that new DT files are using that? We can always use a more precise
>>>>>> compatible for quirks.
>>>>>> 
>>>>> 
>>>>> How about keeping it simple and tied to arm gic versions
>>>>> arm,gicv1, arm,gicv2, arm,gicv2ve
>>>> 
>>>> That's a variation on the same theme. As for GICv2, we don't need to
>>>> distinguish between having the Virtualization Extentions, the binding
>>>> already allows you to tell one from the other.
>>>> 
>>> So if there be just 2 types of gic, it would be simple.
>> 
>> Not exactly. We just happen to support two revisions of the GIC
>> architecture with the same binding. GICv3 has an entierely separate
>> binding.
>> 
>>> gicv1 - 2 address sets (gicc and gicd)
>> 
>> Yes.
>> 
>>> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?
>> 
>> No.
>> 
>> The presence of the GICV, GICH and maintenance interrupt are indicative
>> of the support for the Virtualization Extentions. GICv2 itself can
>> perfectly be built without it.
>
> then does gicv2-ve makes sense ?

Read what I just wrote. You find the GICV region, you have the VE
extensions. You don't find them, they are not present. No need for an
overloaded compatible string, they both conform to the same
*Architecture Spec*.

	M.
-- 
Jazz is not dead. It just smells funny.

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:42:56 am BST, armdev <armdev.ftm@gmail.com> wrote:
> On 10-Apr-2014, at 4:11 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>
>> On Thu, Apr 10 2014 at 11:30:41 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>> On 10-Apr-2014, at 3:51 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>> 
>>>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev <armdev.ftm@gmail.com> wrote:
>>>>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>>>> 
>>>>>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>>>>> This patch declare coretex-a7's irqchip to initialze gic from dt
>>>>>>> with "arm,cortex-a7-gic" data.
>>>>>>> 
>>>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>>>> ---
>>>>>>> drivers/irqchip/irq-gic.c | 1 +
>>>>>>> 1 file changed, 1 insertion(+)
>>>>>>> 
>>>>>>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>>>>>>> index 4300b66..8e906e4 100644
>>>>>>> --- a/drivers/irqchip/irq-gic.c
>>>>>>> +++ b/drivers/irqchip/irq-gic.c
>>>>>>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
>>>>>>> }
>>>>>>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
>>>>>>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
>>>>>>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
>>>>>>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
>>>>>>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>>>>>> 
>>>>>> Frankly, this patch adds no value. Are we going to add
>>>>>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
>>>>>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
>>>>>> 
>>>>>> Instead, how about defining a generic "arm,gic" property, and mandate
>>>>>> that new DT files are using that? We can always use a more precise
>>>>>> compatible for quirks.
>>>>>> 
>>>>> 
>>>>> How about keeping it simple and tied to arm gic versions
>>>>> arm,gicv1, arm,gicv2, arm,gicv2ve
>>>> 
>>>> That's a variation on the same theme. As for GICv2, we don't need to
>>>> distinguish between having the Virtualization Extentions, the binding
>>>> already allows you to tell one from the other.
>>>> 
>>> So if there be just 2 types of gic, it would be simple.
>> 
>> Not exactly. We just happen to support two revisions of the GIC
>> architecture with the same binding. GICv3 has an entierely separate
>> binding.
>> 
>>> gicv1 - 2 address sets (gicc and gicd)
>> 
>> Yes.
>> 
>>> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right?
>> 
>> No.
>> 
>> The presence of the GICV, GICH and maintenance interrupt are indicative
>> of the support for the Virtualization Extentions. GICv2 itself can
>> perfectly be built without it.
>
> then does gicv2-ve makes sense ?

Read what I just wrote. You find the GICV region, you have the VE
extensions. You don't find them, they are not present. No need for an
overloaded compatible string, they both conform to the same
*Architecture Spec*.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

On 04/10/2014 06:51 PM, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>> from Main ID register.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>> index 5eead53..36d3db6 100644
>> --- a/arch/arm/mach-exynos/hotplug.c
>> +++ b/arch/arm/mach-exynos/hotplug.c
>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>  	int primary_part = 0;
>>  
>>  	/*
>> -	 * we're ready for shutdown now, so do it.
>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
>> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>  	 * number by reading the Main ID register and then perform the
>>  	 * appropriate sequence for entering low power.
>>  	 */
>>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
> 
> While you're touching that code, how about using:
> 
>       primary_part = read_cpuid(CPUID_ID);

Or, 
I suggest read_cpuid_part_number() instead of assembler directly.

	primary_part = read_cpuid_part_number();

> 
>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>> +
>> +	/*
>> +	 * Main ID register of Cortex series
>> +	 * - Cortex-a7  : 0x410F_C07x
>> +	 * - Cortex-a15 : 0x410F_C0Fx
>> +	 */
>> +	primary_part = primary_part & 0xfff0;
>> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)
> 
> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7

OK I'll use this defined constant as following:

	switch (primary_part)
	case ARM_CPU_PART_CORTEX_A7:
	case ARM_CPU_PART_CORTEX_A15:
		cpu_enter_lowpower_a15();
		break;
	default:
		cpu_enter_lowpower_a9();
		break;
	}

> 
>>  		cpu_enter_lowpower_a15();
>>  	else
>>  		cpu_enter_lowpower_a9();
> 

Best Regards,
Chanwoo Choi

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

On 04/10/2014 06:51 PM, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>> from Main ID register.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>> index 5eead53..36d3db6 100644
>> --- a/arch/arm/mach-exynos/hotplug.c
>> +++ b/arch/arm/mach-exynos/hotplug.c
>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>  	int primary_part = 0;
>>  
>>  	/*
>> -	 * we're ready for shutdown now, so do it.
>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
>> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>  	 * number by reading the Main ID register and then perform the
>>  	 * appropriate sequence for entering low power.
>>  	 */
>>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
> 
> While you're touching that code, how about using:
> 
>       primary_part = read_cpuid(CPUID_ID);

Or, 
I suggest read_cpuid_part_number() instead of assembler directly.

	primary_part = read_cpuid_part_number();

> 
>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>> +
>> +	/*
>> +	 * Main ID register of Cortex series
>> +	 * - Cortex-a7  : 0x410F_C07x
>> +	 * - Cortex-a15 : 0x410F_C0Fx
>> +	 */
>> +	primary_part = primary_part & 0xfff0;
>> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)
> 
> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7

OK I'll use this defined constant as following:

	switch (primary_part)
	case ARM_CPU_PART_CORTEX_A7:
	case ARM_CPU_PART_CORTEX_A15:
		cpu_enter_lowpower_a15();
		break;
	default:
		cpu_enter_lowpower_a9();
		break;
	}

> 
>>  		cpu_enter_lowpower_a15();
>>  	else
>>  		cpu_enter_lowpower_a9();
> 

Best Regards,
Chanwoo Choi

[PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

On 04/10/2014 06:51 PM, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>> from Main ID register.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>> index 5eead53..36d3db6 100644
>> --- a/arch/arm/mach-exynos/hotplug.c
>> +++ b/arch/arm/mach-exynos/hotplug.c
>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>  	int primary_part = 0;
>>  
>>  	/*
>> -	 * we're ready for shutdown now, so do it.
>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
>> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>  	 * number by reading the Main ID register and then perform the
>>  	 * appropriate sequence for entering low power.
>>  	 */
>>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
> 
> While you're touching that code, how about using:
> 
>       primary_part = read_cpuid(CPUID_ID);

Or, 
I suggest read_cpuid_part_number() instead of assembler directly.

	primary_part = read_cpuid_part_number();

> 
>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>> +
>> +	/*
>> +	 * Main ID register of Cortex series
>> +	 * - Cortex-a7  : 0x410F_C07x
>> +	 * - Cortex-a15 : 0x410F_C0Fx
>> +	 */
>> +	primary_part = primary_part & 0xfff0;
>> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)
> 
> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7

OK I'll use this defined constant as following:

	switch (primary_part)
	case ARM_CPU_PART_CORTEX_A7:
	case ARM_CPU_PART_CORTEX_A15:
		cpu_enter_lowpower_a15();
		break;
	default:
		cpu_enter_lowpower_a9();
		break;
	}

> 
>>  		cpu_enter_lowpower_a15();
>>  	else
>>  		cpu_enter_lowpower_a9();
> 

Best Regards,
Chanwoo Choi

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:56:33 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> On 04/10/2014 06:51 PM, Marc Zyngier wrote:
>> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>>> from Main ID register.
>>>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>>> index 5eead53..36d3db6 100644
>>> --- a/arch/arm/mach-exynos/hotplug.c
>>> +++ b/arch/arm/mach-exynos/hotplug.c
>>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>>  	int primary_part = 0;
>>>  
>>>  	/*
>>> -	 * we're ready for shutdown now, so do it.
>>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>>> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
>>> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>>  	 * number by reading the Main ID register and then perform the
>>>  	 * appropriate sequence for entering low power.
>>>  	 */
>>>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>> 
>> While you're touching that code, how about using:
>> 
>>       primary_part = read_cpuid(CPUID_ID);
>
> Or, 
> I suggest read_cpuid_part_number() instead of assembler directly.
>
> 	primary_part = read_cpuid_part_number();

Yup, even better.

>> 
>>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>>> +
>>> +	/*
>>> +	 * Main ID register of Cortex series
>>> +	 * - Cortex-a7  : 0x410F_C07x
>>> +	 * - Cortex-a15 : 0x410F_C0Fx
>>> +	 */
>>> +	primary_part = primary_part & 0xfff0;
>>> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)
>> 
>> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7
>
> OK I'll use this defined constant as following:
>
> 	switch (primary_part)
> 	case ARM_CPU_PART_CORTEX_A7:
> 	case ARM_CPU_PART_CORTEX_A15:
> 		cpu_enter_lowpower_a15();
> 		break;
> 	default:
> 		cpu_enter_lowpower_a9();
> 		break;
> 	}

Looks good.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:56:33 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> On 04/10/2014 06:51 PM, Marc Zyngier wrote:
>> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>>> from Main ID register.
>>>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>>> index 5eead53..36d3db6 100644
>>> --- a/arch/arm/mach-exynos/hotplug.c
>>> +++ b/arch/arm/mach-exynos/hotplug.c
>>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>>  	int primary_part = 0;
>>>  
>>>  	/*
>>> -	 * we're ready for shutdown now, so do it.
>>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>>> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
>>> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>>  	 * number by reading the Main ID register and then perform the
>>>  	 * appropriate sequence for entering low power.
>>>  	 */
>>>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>> 
>> While you're touching that code, how about using:
>> 
>>       primary_part = read_cpuid(CPUID_ID);
>
> Or, 
> I suggest read_cpuid_part_number() instead of assembler directly.
>
> 	primary_part = read_cpuid_part_number();

Yup, even better.

>> 
>>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>>> +
>>> +	/*
>>> +	 * Main ID register of Cortex series
>>> +	 * - Cortex-a7  : 0x410F_C07x
>>> +	 * - Cortex-a15 : 0x410F_C0Fx
>>> +	 */
>>> +	primary_part = primary_part & 0xfff0;
>>> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)
>> 
>> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7
>
> OK I'll use this defined constant as following:
>
> 	switch (primary_part)
> 	case ARM_CPU_PART_CORTEX_A7:
> 	case ARM_CPU_PART_CORTEX_A15:
> 		cpu_enter_lowpower_a15();
> 		break;
> 	default:
> 		cpu_enter_lowpower_a9();
> 		break;
> 	}

Looks good.

	M.
-- 
Jazz is not dead. It just smells funny.

[PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Marc Zyngier]

On Thu, Apr 10 2014 at 11:56:33 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> On 04/10/2014 06:51 PM, Marc Zyngier wrote:
>> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>>> from Main ID register.
>>>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>>> index 5eead53..36d3db6 100644
>>> --- a/arch/arm/mach-exynos/hotplug.c
>>> +++ b/arch/arm/mach-exynos/hotplug.c
>>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>>  	int primary_part = 0;
>>>  
>>>  	/*
>>> -	 * we're ready for shutdown now, so do it.
>>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>>> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
>>> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>>  	 * number by reading the Main ID register and then perform the
>>>  	 * appropriate sequence for entering low power.
>>>  	 */
>>>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>> 
>> While you're touching that code, how about using:
>> 
>>       primary_part = read_cpuid(CPUID_ID);
>
> Or, 
> I suggest read_cpuid_part_number() instead of assembler directly.
>
> 	primary_part = read_cpuid_part_number();

Yup, even better.

>> 
>>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>>> +
>>> +	/*
>>> +	 * Main ID register of Cortex series
>>> +	 * - Cortex-a7  : 0x410F_C07x
>>> +	 * - Cortex-a15 : 0x410F_C0Fx
>>> +	 */
>>> +	primary_part = primary_part & 0xfff0;
>>> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)
>> 
>> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7
>
> OK I'll use this defined constant as following:
>
> 	switch (primary_part)
> 	case ARM_CPU_PART_CORTEX_A7:
> 	case ARM_CPU_PART_CORTEX_A15:
> 		cpu_enter_lowpower_a15();
> 		break;
> 	default:
> 		cpu_enter_lowpower_a9();
> 		break;
> 	}

Looks good.

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Mark Rutland]

On Thu, Apr 10, 2014 at 11:04:59AM +0100, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> > This patch declare coretex-a7's irqchip to initialze gic from dt
> > with "arm,cortex-a7-gic" data.
> >
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >  drivers/irqchip/irq-gic.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > index 4300b66..8e906e4 100644
> > --- a/drivers/irqchip/irq-gic.c
> > +++ b/drivers/irqchip/irq-gic.c
> > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
> >  }
> >  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
> >  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
> > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
> 
> Frankly, this patch adds no value. Are we going to add
> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
> 
> Instead, how about defining a generic "arm,gic" property, and mandate
> that new DT files are using that? We can always use a more precise
> compatible for quirks.

Nit: s/property/compatible/

As mentioned elsewhere, "arm,gic-v2" would seem to fit the bill (and we
can have "arm,gic" or "arm,gic-v1" for v1).

> Mark, what do you think? I think this has been discussed in the past
> already.

It's been repeatedly brought up and agreed on, it's just that no-one's
implemented it. I agree that having an "arm,gic-v2" binding that people
can place in their compatible list is a sensible thing to do, and I'd be
happy to Ack patches implementing it.

Cheers,
Mark.

Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Mark Rutland]

On Thu, Apr 10, 2014 at 11:04:59AM +0100, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> > This patch declare coretex-a7's irqchip to initialze gic from dt
> > with "arm,cortex-a7-gic" data.
> >
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >  drivers/irqchip/irq-gic.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > index 4300b66..8e906e4 100644
> > --- a/drivers/irqchip/irq-gic.c
> > +++ b/drivers/irqchip/irq-gic.c
> > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
> >  }
> >  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
> >  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
> > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
> 
> Frankly, this patch adds no value. Are we going to add
> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
> 
> Instead, how about defining a generic "arm,gic" property, and mandate
> that new DT files are using that? We can always use a more precise
> compatible for quirks.

Nit: s/property/compatible/

As mentioned elsewhere, "arm,gic-v2" would seem to fit the bill (and we
can have "arm,gic" or "arm,gic-v1" for v1).

> Mark, what do you think? I think this has been discussed in the past
> already.

It's been repeatedly brought up and agreed on, it's just that no-one's
implemented it. I agree that having an "arm,gic-v2" binding that people
can place in their compatible list is a sensible thing to do, and I'd be
happy to Ack patches implementing it.

Cheers,
Mark.

[PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt

[Mark Rutland]

On Thu, Apr 10, 2014 at 11:04:59AM +0100, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> > This patch declare coretex-a7's irqchip to initialze gic from dt
> > with "arm,cortex-a7-gic" data.
> >
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >  drivers/irqchip/irq-gic.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > index 4300b66..8e906e4 100644
> > --- a/drivers/irqchip/irq-gic.c
> > +++ b/drivers/irqchip/irq-gic.c
> > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
> >  }
> >  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
> >  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
> > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
> >  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
> 
> Frankly, this patch adds no value. Are we going to add
> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic",
> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores...
> 
> Instead, how about defining a generic "arm,gic" property, and mandate
> that new DT files are using that? We can always use a more precise
> compatible for quirks.

Nit: s/property/compatible/

As mentioned elsewhere, "arm,gic-v2" would seem to fit the bill (and we
can have "arm,gic" or "arm,gic-v1" for v1).

> Mark, what do you think? I think this has been discussed in the past
> already.

It's been repeatedly brought up and agreed on, it's just that no-one's
implemented it. I agree that having an "arm,gic-v2" binding that people
can place in their compatible list is a sensible thing to do, and I'd be
happy to Ack patches implementing it.

Cheers,
Mark.

Re: [PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Linus Walleij]

On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:

> From: Tomasz Figa <t.figa@samsung.com>
>
> This patch adds driver data (bank list and EINT layout) for Exynos3250
> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
> ports. There are 23 general port groups.
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Ugh can Tomasz send out his patches himself, I get confused...
It was also sent two times, the second time with CC:s added.
Tomasz, shall I merge this?

Yours,
Linus Walleij

Re: [PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Linus Walleij]

On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:

> From: Tomasz Figa <t.figa@samsung.com>
>
> This patch adds driver data (bank list and EINT layout) for Exynos3250
> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
> ports. There are 23 general port groups.
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Ugh can Tomasz send out his patches himself, I get confused...
It was also sent two times, the second time with CC:s added.
Tomasz, shall I merge this?

Yours,
Linus Walleij

[PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Linus Walleij]

On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:

> From: Tomasz Figa <t.figa@samsung.com>
>
> This patch adds driver data (bank list and EINT layout) for Exynos3250
> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
> ports. There are 23 general port groups.
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Ugh can Tomasz send out his patches himself, I get confused...
It was also sent two times, the second time with CC:s added.
Tomasz, shall I merge this?

Yours,
Linus Walleij

Re: [PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Tomasz Figa]

Hi,

On 10.04.2014 20:42, Linus Walleij wrote:
> On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>
>> From: Tomasz Figa <t.figa@samsung.com>
>>
>> This patch adds driver data (bank list and EINT layout) for Exynos3250
>> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
>> ports. There are 23 general port groups.
>>
>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>
> Ugh can Tomasz send out his patches himself, I get confused...
> It was also sent two times, the second time with CC:s added.
> Tomasz, shall I merge this?

I'm fine with this patch being sent by Chanwoo, although he should have 
probably added his sign-off to the list, as the person sending it.

Chanwoo, can you make sure that there is your sign-off on all the 
patches from this series?

Best regards,
Tomasz

Re: [PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Tomasz Figa]

Hi,

On 10.04.2014 20:42, Linus Walleij wrote:
> On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>
>> From: Tomasz Figa <t.figa@samsung.com>
>>
>> This patch adds driver data (bank list and EINT layout) for Exynos3250
>> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
>> ports. There are 23 general port groups.
>>
>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>
> Ugh can Tomasz send out his patches himself, I get confused...
> It was also sent two times, the second time with CC:s added.
> Tomasz, shall I merge this?

I'm fine with this patch being sent by Chanwoo, although he should have 
probably added his sign-off to the list, as the person sending it.

Chanwoo, can you make sure that there is your sign-off on all the 
patches from this series?

Best regards,
Tomasz

[PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Tomasz Figa]

Hi,

On 10.04.2014 20:42, Linus Walleij wrote:
> On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>
>> From: Tomasz Figa <t.figa@samsung.com>
>>
>> This patch adds driver data (bank list and EINT layout) for Exynos3250
>> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
>> ports. There are 23 general port groups.
>>
>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>
> Ugh can Tomasz send out his patches himself, I get confused...
> It was also sent two times, the second time with CC:s added.
> Tomasz, shall I merge this?

I'm fine with this patch being sent by Chanwoo, although he should have 
probably added his sign-off to the list, as the person sending it.

Chanwoo, can you make sure that there is your sign-off on all the 
patches from this series?

Best regards,
Tomasz

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

On 04/10/2014 09:07 PM, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 11:56:33 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> On 04/10/2014 06:51 PM, Marc Zyngier wrote:
>>> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>>>> from Main ID register.
>>>>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>> ---
>>>>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>>>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>>>> index 5eead53..36d3db6 100644
>>>> --- a/arch/arm/mach-exynos/hotplug.c
>>>> +++ b/arch/arm/mach-exynos/hotplug.c
>>>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>>>  	int primary_part = 0;
>>>>  
>>>>  	/*
>>>> -	 * we're ready for shutdown now, so do it.
>>>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>>>> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
>>>> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>>>  	 * number by reading the Main ID register and then perform the
>>>>  	 * appropriate sequence for entering low power.
>>>>  	 */
>>>>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>>>
>>> While you're touching that code, how about using:
>>>
>>>       primary_part = read_cpuid(CPUID_ID);
>>
>> Or, 
>> I suggest read_cpuid_part_number() instead of assembler directly.
>>
>> 	primary_part = read_cpuid_part_number();
> 
> Yup, even better.
> 
>>>
>>>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>>>> +
>>>> +	/*
>>>> +	 * Main ID register of Cortex series
>>>> +	 * - Cortex-a7  : 0x410F_C07x
>>>> +	 * - Cortex-a15 : 0x410F_C0Fx
>>>> +	 */
>>>> +	primary_part = primary_part & 0xfff0;
>>>> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)
>>>
>>> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7
>>
>> OK I'll use this defined constant as following:
>>
>> 	switch (primary_part)
>> 	case ARM_CPU_PART_CORTEX_A7:
>> 	case ARM_CPU_PART_CORTEX_A15:
>> 		cpu_enter_lowpower_a15();
>> 		break;
>> 	default:
>> 		cpu_enter_lowpower_a9();
>> 		break;
>> 	}
> 
> Looks good.
> 

Thanks for your review.

Best Regards,
Chanwoo Choi

Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

On 04/10/2014 09:07 PM, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 11:56:33 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> On 04/10/2014 06:51 PM, Marc Zyngier wrote:
>>> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>>>> from Main ID register.
>>>>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>> ---
>>>>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>>>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>>>> index 5eead53..36d3db6 100644
>>>> --- a/arch/arm/mach-exynos/hotplug.c
>>>> +++ b/arch/arm/mach-exynos/hotplug.c
>>>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>>>  	int primary_part = 0;
>>>>  
>>>>  	/*
>>>> -	 * we're ready for shutdown now, so do it.
>>>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>>>> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
>>>> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>>>  	 * number by reading the Main ID register and then perform the
>>>>  	 * appropriate sequence for entering low power.
>>>>  	 */
>>>>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>>>
>>> While you're touching that code, how about using:
>>>
>>>       primary_part = read_cpuid(CPUID_ID);
>>
>> Or, 
>> I suggest read_cpuid_part_number() instead of assembler directly.
>>
>> 	primary_part = read_cpuid_part_number();
> 
> Yup, even better.
> 
>>>
>>>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>>>> +
>>>> +	/*
>>>> +	 * Main ID register of Cortex series
>>>> +	 * - Cortex-a7  : 0x410F_C07x
>>>> +	 * - Cortex-a15 : 0x410F_C0Fx
>>>> +	 */
>>>> +	primary_part = primary_part & 0xfff0;
>>>> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)
>>>
>>> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7
>>
>> OK I'll use this defined constant as following:
>>
>> 	switch (primary_part)
>> 	case ARM_CPU_PART_CORTEX_A7:
>> 	case ARM_CPU_PART_CORTEX_A15:
>> 		cpu_enter_lowpower_a15();
>> 		break;
>> 	default:
>> 		cpu_enter_lowpower_a9();
>> 		break;
>> 	}
> 
> Looks good.
> 

Thanks for your review.

Best Regards,
Chanwoo Choi

[PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

On 04/10/2014 09:07 PM, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 11:56:33 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> On 04/10/2014 06:51 PM, Marc Zyngier wrote:
>>> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>>>> from Main ID register.
>>>>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>> ---
>>>>  arch/arm/mach-exynos/hotplug.c | 13 ++++++++++---
>>>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>>>> index 5eead53..36d3db6 100644
>>>> --- a/arch/arm/mach-exynos/hotplug.c
>>>> +++ b/arch/arm/mach-exynos/hotplug.c
>>>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>>>  	int primary_part = 0;
>>>>  
>>>>  	/*
>>>> -	 * we're ready for shutdown now, so do it.
>>>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>>>> +	 * we're ready for shutdown now, so do it. Exynos4 is A9 based
>>>> +	 * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>>>  	 * number by reading the Main ID register and then perform the
>>>>  	 * appropriate sequence for entering low power.
>>>>  	 */
>>>>  	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>>>
>>> While you're touching that code, how about using:
>>>
>>>       primary_part = read_cpuid(CPUID_ID);
>>
>> Or, 
>> I suggest read_cpuid_part_number() instead of assembler directly.
>>
>> 	primary_part = read_cpuid_part_number();
> 
> Yup, even better.
> 
>>>
>>>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>>>> +
>>>> +	/*
>>>> +	 * Main ID register of Cortex series
>>>> +	 * - Cortex-a7  : 0x410F_C07x
>>>> +	 * - Cortex-a15 : 0x410F_C0Fx
>>>> +	 */
>>>> +	primary_part = primary_part & 0xfff0;
>>>> +	if (primary_part == 0xc0f0 || primary_part == 0xc070)
>>>
>>> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7
>>
>> OK I'll use this defined constant as following:
>>
>> 	switch (primary_part)
>> 	case ARM_CPU_PART_CORTEX_A7:
>> 	case ARM_CPU_PART_CORTEX_A15:
>> 		cpu_enter_lowpower_a15();
>> 		break;
>> 	default:
>> 		cpu_enter_lowpower_a9();
>> 		break;
>> 	}
> 
> Looks good.
> 

Thanks for your review.

Best Regards,
Chanwoo Choi

Re: [PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Chanwoo Choi]

Hi, 

On 04/11/2014 04:17 AM, Tomasz Figa wrote:
> Hi,
> 
> On 10.04.2014 20:42, Linus Walleij wrote:
>> On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>
>>> From: Tomasz Figa <t.figa@samsung.com>
>>>
>>> This patch adds driver data (bank list and EINT layout) for Exynos3250
>>> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
>>> ports. There are 23 general port groups.
>>>
>>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>
>> Ugh can Tomasz send out his patches himself, I get confused...
>> It was also sent two times, the second time with CC:s added.
>> Tomasz, shall I merge this?
> 
> I'm fine with this patch being sent by Chanwoo, although he should have probably added his sign-off to the list, as the person sending it.
> 
> Chanwoo, can you make sure that there is your sign-off on all the patches from this series?
> 

OK, I'll add my sign-off to all the patches on next posting(v2).

Best Regards,
Chanwoo Choi

Re: [PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Chanwoo Choi]

Hi, 

On 04/11/2014 04:17 AM, Tomasz Figa wrote:
> Hi,
> 
> On 10.04.2014 20:42, Linus Walleij wrote:
>> On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>
>>> From: Tomasz Figa <t.figa@samsung.com>
>>>
>>> This patch adds driver data (bank list and EINT layout) for Exynos3250
>>> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
>>> ports. There are 23 general port groups.
>>>
>>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>
>> Ugh can Tomasz send out his patches himself, I get confused...
>> It was also sent two times, the second time with CC:s added.
>> Tomasz, shall I merge this?
> 
> I'm fine with this patch being sent by Chanwoo, although he should have probably added his sign-off to the list, as the person sending it.
> 
> Chanwoo, can you make sure that there is your sign-off on all the patches from this series?
> 

OK, I'll add my sign-off to all the patches on next posting(v2).

Best Regards,
Chanwoo Choi

[PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250

[Chanwoo Choi]

Hi, 

On 04/11/2014 04:17 AM, Tomasz Figa wrote:
> Hi,
> 
> On 10.04.2014 20:42, Linus Walleij wrote:
>> On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>
>>> From: Tomasz Figa <t.figa@samsung.com>
>>>
>>> This patch adds driver data (bank list and EINT layout) for Exynos3250
>>> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
>>> ports. There are 23 general port groups.
>>>
>>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>
>> Ugh can Tomasz send out his patches himself, I get confused...
>> It was also sent two times, the second time with CC:s added.
>> Tomasz, shall I merge this?
> 
> I'm fine with this patch being sent by Chanwoo, although he should have probably added his sign-off to the list, as the person sending it.
> 
> Chanwoo, can you make sure that there is your sign-off on all the patches from this series?
> 

OK, I'll add my sign-off to all the patches on next posting(v2).

Best Regards,
Chanwoo Choi

Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Chanwoo Choi]

Hi,

On 04/10/2014 06:43 PM, Arnd Bergmann wrote:
> On Thursday 10 April 2014 18:28:18 Chanwoo Choi wrote:
>> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
>> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
>> dual cores and has a target speed of 1.0GHz.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>  arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
>>  arch/arm/mach-exynos/exynos.c            |  1 +
>>  arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
>>  3 files changed, 33 insertions(+)
>>
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index fc8bf18..6da8a68 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -11,6 +11,17 @@ if ARCH_EXYNOS
>>  
>>  menu "SAMSUNG EXYNOS SoCs Support"
>>  
>> +config ARCH_EXYNOS3
>> +	bool "SAMSUNG EXYNOS3"
>> +	select ARM_AMBA
>> +	select CLKSRC_OF
>> +	select HAVE_ARM_SCU if SMP
>> +	select HAVE_SMP
>> +	select PINCTRL
>> +	select PM_GENERIC_DOMAINS if PM_RUNTIME
>> +	help
>> +	  Samsung EXYNOS3 SoCs based systems
>> +
> 
> Isn't S5PV210 also called an Exynos3 these days? Are we going to get
> any conflicts here when merging that code into Exynos as Tomasz has
> suggested in the past?

I knew. But, S5PV210/S5PC110 has not yet included in Exynos3 category on mainline.
Need opinion of Exynos SoC Maintainer to clear this ambiguous stuff.

Dear Kukjin and Tomasz,
I need your opinion about this patch.

Best Regards,
Chanwoo Choi

[PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Chanwoo Choi]

Hi,

On 04/10/2014 06:43 PM, Arnd Bergmann wrote:
> On Thursday 10 April 2014 18:28:18 Chanwoo Choi wrote:
>> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
>> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
>> dual cores and has a target speed of 1.0GHz.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>  arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
>>  arch/arm/mach-exynos/exynos.c            |  1 +
>>  arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
>>  3 files changed, 33 insertions(+)
>>
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index fc8bf18..6da8a68 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -11,6 +11,17 @@ if ARCH_EXYNOS
>>  
>>  menu "SAMSUNG EXYNOS SoCs Support"
>>  
>> +config ARCH_EXYNOS3
>> +	bool "SAMSUNG EXYNOS3"
>> +	select ARM_AMBA
>> +	select CLKSRC_OF
>> +	select HAVE_ARM_SCU if SMP
>> +	select HAVE_SMP
>> +	select PINCTRL
>> +	select PM_GENERIC_DOMAINS if PM_RUNTIME
>> +	help
>> +	  Samsung EXYNOS3 SoCs based systems
>> +
> 
> Isn't S5PV210 also called an Exynos3 these days? Are we going to get
> any conflicts here when merging that code into Exynos as Tomasz has
> suggested in the past?

I knew. But, S5PV210/S5PC110 has not yet included in Exynos3 category on mainline.
Need opinion of Exynos SoC Maintainer to clear this ambiguous stuff.

Dear Kukjin and Tomasz,
I need your opinion about this patch.

Best Regards,
Chanwoo Choi

Re: [PATCH 03/27] ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

[Chanwoo Choi]

Dear Arnd and Kukjin,

On 04/10/2014 06:46 PM, Arnd Bergmann wrote:
> On Thursday 10 April 2014 18:28:20 Chanwoo Choi wrote:
>> This patch add memory mapping for PMU (Power Management Unit) which is used
>> for power control of Exynos3250.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> 
> Same thing as for the SRAM here, can you work on making this a proper
> driver instead?
> 

As Chanho Park said, Sachin already submitted the DT support[1] for SYSRAM area.
[1] : http://www.spinics.net/lists/linux-samsung-soc/msg27647.html

But, this patch has not yet to merge git repository(linux-samsung.git, arm-soc.git).
So, I'll make a driver to handle PMU memory mapping after Sachin's patch is merged.

Best Regards,
Chanwoo Choi

[PATCH 03/27] ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

[Chanwoo Choi]

Dear Arnd and Kukjin,

On 04/10/2014 06:46 PM, Arnd Bergmann wrote:
> On Thursday 10 April 2014 18:28:20 Chanwoo Choi wrote:
>> This patch add memory mapping for PMU (Power Management Unit) which is used
>> for power control of Exynos3250.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> 
> Same thing as for the SRAM here, can you work on making this a proper
> driver instead?
> 

As Chanho Park said, Sachin already submitted the DT support[1] for SYSRAM area.
[1] : http://www.spinics.net/lists/linux-samsung-soc/msg27647.html

But, this patch has not yet to merge git repository(linux-samsung.git, arm-soc.git).
So, I'll make a driver to handle PMU memory mapping after Sachin's patch is merged.

Best Regards,
Chanwoo Choi

Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Chanwoo Choi]

Dear Kukjin and Tomasz,

On 04/11/2014 10:31 AM, Chanwoo Choi wrote:
> Hi,
> 
> On 04/10/2014 06:43 PM, Arnd Bergmann wrote:
>> On Thursday 10 April 2014 18:28:18 Chanwoo Choi wrote:
>>> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
>>> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
>>> dual cores and has a target speed of 1.0GHz.
>>>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
>>>  arch/arm/mach-exynos/exynos.c            |  1 +
>>>  arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
>>>  3 files changed, 33 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>>> index fc8bf18..6da8a68 100644
>>> --- a/arch/arm/mach-exynos/Kconfig
>>> +++ b/arch/arm/mach-exynos/Kconfig
>>> @@ -11,6 +11,17 @@ if ARCH_EXYNOS
>>>  
>>>  menu "SAMSUNG EXYNOS SoCs Support"
>>>  
>>> +config ARCH_EXYNOS3
>>> +	bool "SAMSUNG EXYNOS3"
>>> +	select ARM_AMBA
>>> +	select CLKSRC_OF
>>> +	select HAVE_ARM_SCU if SMP
>>> +	select HAVE_SMP
>>> +	select PINCTRL
>>> +	select PM_GENERIC_DOMAINS if PM_RUNTIME
>>> +	help
>>> +	  Samsung EXYNOS3 SoCs based systems
>>> +
>>
>> Isn't S5PV210 also called an Exynos3 these days? Are we going to get
>> any conflicts here when merging that code into Exynos as Tomasz has
>> suggested in the past?
> 
> I knew. But, S5PV210/S5PC110 has not yet included in Exynos3 category on mainline.
> Need opinion of Exynos SoC Maintainer to clear this ambiguous stuff.
> 
> Dear Kukjin and Tomasz,
> I need your opinion about this patch.
> 

Please review this patch and reply about Arnd's comment.

Best Regards,
Chanwoo Choi

[PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID

[Chanwoo Choi]

Dear Kukjin and Tomasz,

On 04/11/2014 10:31 AM, Chanwoo Choi wrote:
> Hi,
> 
> On 04/10/2014 06:43 PM, Arnd Bergmann wrote:
>> On Thursday 10 April 2014 18:28:18 Chanwoo Choi wrote:
>>> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
>>> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
>>> dual cores and has a target speed of 1.0GHz.
>>>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
>>>  arch/arm/mach-exynos/exynos.c            |  1 +
>>>  arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
>>>  3 files changed, 33 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>>> index fc8bf18..6da8a68 100644
>>> --- a/arch/arm/mach-exynos/Kconfig
>>> +++ b/arch/arm/mach-exynos/Kconfig
>>> @@ -11,6 +11,17 @@ if ARCH_EXYNOS
>>>  
>>>  menu "SAMSUNG EXYNOS SoCs Support"
>>>  
>>> +config ARCH_EXYNOS3
>>> +	bool "SAMSUNG EXYNOS3"
>>> +	select ARM_AMBA
>>> +	select CLKSRC_OF
>>> +	select HAVE_ARM_SCU if SMP
>>> +	select HAVE_SMP
>>> +	select PINCTRL
>>> +	select PM_GENERIC_DOMAINS if PM_RUNTIME
>>> +	help
>>> +	  Samsung EXYNOS3 SoCs based systems
>>> +
>>
>> Isn't S5PV210 also called an Exynos3 these days? Are we going to get
>> any conflicts here when merging that code into Exynos as Tomasz has
>> suggested in the past?
> 
> I knew. But, S5PV210/S5PC110 has not yet included in Exynos3 category on mainline.
> Need opinion of Exynos SoC Maintainer to clear this ambiguous stuff.
> 
> Dear Kukjin and Tomasz,
> I need your opinion about this patch.
> 

Please review this patch and reply about Arnd's comment.

Best Regards,
Chanwoo Choi

[PATCH 00/27] Support new Exynos3250 SoC based on Cortex-A7 dual core

[Chanwoo Choi]

This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
and provides the best performance features.

This patchset include some patches such as:
- Support secondary CPU of Exynos3250 (cpu up/down)
- Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/pwm/amba
- Support the gpio control for Exynos3250 using pinctrl
- Support the clock control for Exynos3250 using common clk framework

Chanwoo Choi (11):
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250
  ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
  irqchip: Declare cortex-a7's irqchip to initialize gic from dt
  ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
  ARM: dts: exynos3250: Add uart dt node to support seiral ports
  ARM: dts: exynos3250: Add MCT dt node
  ARM: dts: exynos3250: Add ADC dt node to read analog raw data
  ARM: dts: exynos3250: Add CPUs dt node for Exynos3250

Hyunhee Kim (1):
  ARM: dts: exynos3250: Add PMU dt data

Inki Dae (2):
  ARM: dts: exynos3250: Add i2c dt node
  ARM: dts: exynos3250: Add power domain dt nodes

Kyungmin Park (2):
  ARM: EXYNOS: Support secondary CPU boot of Exynos4212
  ARM: dts: exynos3250: Add Mobile Storage Host Card

Tomasz Figa (11):
  pinctrl: exynos: Add driver data for Exynos3250
  clk: samsung: exynos3250: Add clocks using common clock framework
  ARM: dts: exynos3250: Add new exynos3250.dtsi file
  ARM: dts: exynos3250: Add GIC dt node for Exynos3250
  ARM: dts: exynos3250: Add pin control device tree data
  ARM: dts: exynos3250: Add device tree nodes for clock controllers
  ARM: dts: exynos3250: Move definitions of external clocks to SoC dtsi
  ARM: dts: exynos3250: Add amba and pdma dt node
  ARM: dts: exynos3250: Add spi dt node to support spi bus
  ARM: dts: exynos3250: Add pwm dt node to support PWM Timer
  ARM: dts: exynos3250: Add RTC dt node

 arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 ++++++++++++++++++
 arch/arm/boot/dts/exynos3250.dtsi         | 410 ++++++++++++++++
 arch/arm/mach-exynos/Kconfig              |  22 +
 arch/arm/mach-exynos/exynos.c             |  18 +
 arch/arm/mach-exynos/firmware.c           |  17 +-
 arch/arm/mach-exynos/hotplug.c            |  13 +-
 arch/arm/mach-exynos/include/mach/map.h   |   2 +
 arch/arm/plat-samsung/include/plat/cpu.h  |  10 +
 drivers/clk/samsung/Makefile              |   1 +
 drivers/clk/samsung/clk-exynos3250.c      | 785 ++++++++++++++++++++++++++++++
 drivers/irqchip/irq-gic.c                 |   1 +
 drivers/pinctrl/pinctrl-exynos.c          |  67 +++
 drivers/pinctrl/pinctrl-samsung.c         |   2 +
 drivers/pinctrl/pinctrl-samsung.h         |   1 +
 include/dt-bindings/clock/exynos3250.h    | 256 ++++++++++
 15 files changed, 2077 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
 create mode 100644 drivers/clk/samsung/clk-exynos3250.c
 create mode 100644 include/dt-bindings/clock/exynos3250.h

-- 
1.8.0

[PATCH 00/27] Support new Exynos3250 SoC based on Cortex-A7 dual core

[Chanwoo Choi]

This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
and provides the best performance features.

This patchset include some patches such as:
- Support secondary CPU of Exynos3250 (cpu up/down)
- Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/pwm/amba
- Support the gpio control for Exynos3250 using pinctrl
- Support the clock control for Exynos3250 using common clk framework

Chanwoo Choi (11):
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250
  ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
  irqchip: Declare cortex-a7's irqchip to initialize gic from dt
  ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
  ARM: dts: exynos3250: Add uart dt node to support seiral ports
  ARM: dts: exynos3250: Add MCT dt node
  ARM: dts: exynos3250: Add ADC dt node to read analog raw data
  ARM: dts: exynos3250: Add CPUs dt node for Exynos3250

Hyunhee Kim (1):
  ARM: dts: exynos3250: Add PMU dt data

Inki Dae (2):
  ARM: dts: exynos3250: Add i2c dt node
  ARM: dts: exynos3250: Add power domain dt nodes

Kyungmin Park (2):
  ARM: EXYNOS: Support secondary CPU boot of Exynos4212
  ARM: dts: exynos3250: Add Mobile Storage Host Card

Tomasz Figa (11):
  pinctrl: exynos: Add driver data for Exynos3250
  clk: samsung: exynos3250: Add clocks using common clock framework
  ARM: dts: exynos3250: Add new exynos3250.dtsi file
  ARM: dts: exynos3250: Add GIC dt node for Exynos3250
  ARM: dts: exynos3250: Add pin control device tree data
  ARM: dts: exynos3250: Add device tree nodes for clock controllers
  ARM: dts: exynos3250: Move definitions of external clocks to SoC dtsi
  ARM: dts: exynos3250: Add amba and pdma dt node
  ARM: dts: exynos3250: Add spi dt node to support spi bus
  ARM: dts: exynos3250: Add pwm dt node to support PWM Timer
  ARM: dts: exynos3250: Add RTC dt node

 arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 ++++++++++++++++++
 arch/arm/boot/dts/exynos3250.dtsi         | 410 ++++++++++++++++
 arch/arm/mach-exynos/Kconfig              |  22 +
 arch/arm/mach-exynos/exynos.c             |  18 +
 arch/arm/mach-exynos/firmware.c           |  17 +-
 arch/arm/mach-exynos/hotplug.c            |  13 +-
 arch/arm/mach-exynos/include/mach/map.h   |   2 +
 arch/arm/plat-samsung/include/plat/cpu.h  |  10 +
 drivers/clk/samsung/Makefile              |   1 +
 drivers/clk/samsung/clk-exynos3250.c      | 785 ++++++++++++++++++++++++++++++
 drivers/irqchip/irq-gic.c                 |   1 +
 drivers/pinctrl/pinctrl-exynos.c          |  67 +++
 drivers/pinctrl/pinctrl-samsung.c         |   2 +
 drivers/pinctrl/pinctrl-samsung.h         |   1 +
 include/dt-bindings/clock/exynos3250.h    | 256 ++++++++++
 15 files changed, 2077 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
 create mode 100644 drivers/clk/samsung/clk-exynos3250.c
 create mode 100644 include/dt-bindings/clock/exynos3250.h

-- 
1.8.0