From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYdZz-0002UV-HW for qemu-devel@nongnu.org; Fri, 11 Apr 2014 11:41:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WYdZt-0004CS-05 for qemu-devel@nongnu.org; Fri, 11 Apr 2014 11:41:23 -0400 Received: from mail-qc0-x22d.google.com ([2607:f8b0:400d:c01::22d]:33328) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYdZs-0004C1-Rg for qemu-devel@nongnu.org; Fri, 11 Apr 2014 11:41:16 -0400 Received: by mail-qc0-f173.google.com with SMTP id r5so5980911qcx.4 for ; Fri, 11 Apr 2014 08:41:16 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 11 Apr 2014 08:40:12 -0700 Message-Id: <1397230827-24222-11-git-send-email-rth@twiddle.net> In-Reply-To: <1397230827-24222-1-git-send-email-rth@twiddle.net> References: <1397230827-24222-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v4 10/25] tcg-aarch64: Use CBZ and CBNZ List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: claudio.fontana@huawei.com A compare and branch against zero happens at the start of every single TB. Reviewed-by: Claudio Fontana Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 5889a98..48a246d 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -270,6 +270,10 @@ enum aarch64_ldst_op_type { /* type of operation */ use the section number of the architecture reference manual in which the instruction group is described. */ typedef enum { + /* Compare and branch (immediate). */ + I3201_CBZ = 0x34000000, + I3201_CBNZ = 0x35000000, + /* Conditional branch (immediate). */ I3202_B_C = 0x54000000, @@ -433,6 +437,12 @@ static inline uint32_t tcg_in32(TCGContext *s) #define tcg_out_insn(S, FMT, OP, ...) \ glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__) +static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rt, int imm19) +{ + tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt); +} + static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn, TCGCond c, int imm19) { @@ -913,8 +923,14 @@ static void tcg_out_brcond(TCGContext *s, TCGMemOp ext, TCGCond c, TCGArg a, { TCGLabel *l = &s->labels[label]; intptr_t offset; + bool need_cmp; - tcg_out_cmp(s, ext, a, b, b_const); + if (b_const && b == 0 && (c == TCG_COND_EQ || c == TCG_COND_NE)) { + need_cmp = false; + } else { + need_cmp = true; + tcg_out_cmp(s, ext, a, b, b_const); + } if (!l->has_value) { tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, label, 0); @@ -925,7 +941,13 @@ static void tcg_out_brcond(TCGContext *s, TCGMemOp ext, TCGCond c, TCGArg a, assert(offset >= -0x40000 && offset < 0x40000); } - tcg_out_insn(s, 3202, B_C, c, offset); + if (need_cmp) { + tcg_out_insn(s, 3202, B_C, c, offset); + } else if (c == TCG_COND_EQ) { + tcg_out_insn(s, 3201, CBZ, ext, a, offset); + } else { + tcg_out_insn(s, 3201, CBNZ, ext, a, offset); + } } static inline void tcg_out_rev(TCGContext *s, TCGType ext, -- 1.9.0