From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45922) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYdZs-0002IB-T0 for qemu-devel@nongnu.org; Fri, 11 Apr 2014 11:41:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WYdZo-00048S-1r for qemu-devel@nongnu.org; Fri, 11 Apr 2014 11:41:16 -0400 Received: from mail-qg0-x234.google.com ([2607:f8b0:400d:c04::234]:33984) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYdZn-000486-V5 for qemu-devel@nongnu.org; Fri, 11 Apr 2014 11:41:12 -0400 Received: by mail-qg0-f52.google.com with SMTP id q107so5663386qgd.11 for ; Fri, 11 Apr 2014 08:41:11 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 11 Apr 2014 08:40:09 -0700 Message-Id: <1397230827-24222-8-git-send-email-rth@twiddle.net> In-Reply-To: <1397230827-24222-1-git-send-email-rth@twiddle.net> References: <1397230827-24222-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v4 07/25] tcg-aarch64: Use adrp in tcg_out_movi List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: claudio.fontana@huawei.com Loading an qemu pointer as an immediate happens often. E.g. - exit_tb $0x7fa8140013 + exit_tb $0x7f81ee0013 ... - : d2800260 mov x0, #0x13 - : f2b50280 movk x0, #0xa814, lsl #16 - : f2c00fe0 movk x0, #0x7f, lsl #32 + : 90ff1000 adrp x0, 0x7f81ee0000 + : 91004c00 add x0, x0, #0x13 Reviewed-by: Claudio Fontana Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index a08f6c7..1337a13 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -294,6 +294,10 @@ typedef enum { I3405_MOVZ = 0x52800000, I3405_MOVK = 0x72800000, + /* PC relative addressing instructions. */ + I3406_ADR = 0x10000000, + I3406_ADRP = 0x90000000, + /* Add/subtract shifted register instructions (without a shift). */ I3502_ADD = 0x0b000000, I3502_ADDS = 0x2b000000, @@ -457,6 +461,12 @@ static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext, tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd); } +static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn, + TCGReg rd, int64_t disp) +{ + tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd); +} + /* This function is for both 3.5.2 (Add/Subtract shifted register), for the rare occasion when we actually want to supply a shift amount. */ static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn, @@ -596,6 +606,19 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, return; } + /* Look for host pointer values within 4G of the PC. This happens + often when loading pointers to QEMU's own data structures. */ + if (type == TCG_TYPE_I64) { + tcg_target_long disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12); + if (disp == sextract64(disp, 0, 21)) { + tcg_out_insn(s, 3406, ADRP, rd, disp); + if (value & 0xfff) { + tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff); + } + return; + } + } + /* Would it take fewer insns to begin with MOVN? For the value and its inverse, count the number of 16-bit lanes that are 0. */ for (i = wantinv = imask = 0; i < 64; i += 16) { -- 1.9.0