From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ian Campbell <ijc@hellion.org.uk>
Date: Sun, 13 Apr 2014 20:55:57 +0100
Subject: [U-Boot] [PATCH v2 1/9] sunxi: initial sun7i clocks and timer
 support.
In-Reply-To: <5330B4C9.10302@schinagl.nl>
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	<1395438866-1193-1-git-send-email-ijc@hellion.org.uk>
	<201403242152.38910.marex@denx.de> <5330B4C9.10302@schinagl.nl>
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On Mon, 2014-03-24 at 23:42 +0100, Olliver Schinagl wrote:
> On 03/24/2014 09:52 PM, Marek Vasut wrote:
> >> +	/* Switch to 24MHz clock while changing PLL1 */
> >> +	writel(AXI_DIV_1 << AXI_DIV_SHIFT |
> >> +	       AHB_DIV_2 << AHB_DIV_SHIFT |
> >> +	       APB0_DIV_1 << APB0_DIV_SHIFT |
> >> +	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
> >> +	       &ccm->cpu_ahb_apb0_cfg);
> >> +	sdelay(20);
> > What is sdelay() function all about ?
> It also is from
> arch/arm/include/asm/arch-sunxi/sys_proto.h
> and I thought all where replaced with udelays

Since these sdelays() are used while we are frobbing around with the
clocks I'm not sure that switching to udelay is possible/wise. sdelay is
documented as:
 * sdelay() - simple spin loop.  Will be constant time as
 *  its generally used in bypass conditions only.  This
 *  is necessary until timers are accessible.

IOW it sounds like it is designed to be used in exactly these
circumstances.

Given the lack of documentation for what is actually required by the
hardware when changing these clocks I'm a bit reluctant to go changing
things.

Ian.