From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46329) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfscE-0001vA-9F for qemu-devel@nongnu.org; Thu, 01 May 2014 11:09:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WfscB-0000Sy-DQ for qemu-devel@nongnu.org; Thu, 01 May 2014 11:09:38 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:47976) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfscB-0000Ry-5o for qemu-devel@nongnu.org; Thu, 01 May 2014 11:09:35 -0400 From: Peter Maydell Date: Thu, 1 May 2014 15:54:57 +0100 Message-Id: <1398956107-7411-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 00/10] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org Nothing earthshattering here, but it does have the patch which actually lets us boot an emulated AArch64 CPU on a board... thanks -- PMM The following changes since commit 051b9980b99dbfba22ea5f79bd3708d513ae121d: Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-6' into staging (2014-05-01 14:17:33 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140501 for you to fetch changes up to f42c5c8ec8aa0e15583487ffee62964830751623: hw/arm/virt: Add support for Cortex-A57 (2014-05-01 15:25:52 +0100) ---------------------------------------------------------------- target-arm queue: * implement XScale cache lockdown cp15 ops * fix v7M CPUID base register * implement WFE and YIELD as yields for A64 * fix A64 "BLR LR" * support Cortex-A57 in virt machine model * a few other minor AArch64 bugfixes ---------------------------------------------------------------- Edgar E. Iglesias (4): target-arm: Make vbar_write 64bit friendly on 32bit hosts target-arm: A64: Handle blr lr target-arm: A64: Fix a typo when declaring TLBI ops target-arm: Correct a comment refering to EL0 Peter Maydell (4): target-arm: Implement XScale cache lockdown operations as NOPs hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv hw/arm/virt: Put GIC register banks on 64K boundaries hw/arm/virt: Add support for Cortex-A57 Rabin Vincent (1): armv7m_nvic: fix CPUID Base Register Rob Herring (1): target-arm: implement WFE/YIELD as a yield for AArch64 hw/arm/virt.c | 93 ++++++++++++++++++++++++++++++---------------- hw/intc/armv7m_nvic.c | 2 +- target-arm/helper.c | 41 +++++++++++++------- target-arm/op_helper.c | 2 +- target-arm/translate-a64.c | 9 ++++- 5 files changed, 99 insertions(+), 48 deletions(-)