From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 16/71] drm/i915/chv: Add DPIO offset for Cherryview. v3 Date: Mon, 12 May 2014 14:27:15 +0300 Message-ID: <1399894035.4454.2.camel@intelbox> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-17-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1701219643==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B08E6E720 for ; Mon, 12 May 2014 04:27:18 -0700 (PDT) In-Reply-To: <1397039349-10639-17-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1701219643== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-rocKL0eAiiHVc0waqIzi" --=-rocKL0eAiiHVc0waqIzi Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote: > From: Chon Ming Lee >=20 > CHV has 2 display phys. First phy (IOSF offset 0x1A) has two channels, > and second phy (IOSF offset 0x12) has single channel. The first phy is > used for port B and port C, while second phy is only for port D. >=20 > v2: Move the pipe to determine which phy to select for > vlv_dpio_read/vlv_dpio_write to another patch. (Daniel) > v3: Rebase the code based on rework on how to calculate DPIO offset. >=20 > Signed-off-by: Chon Ming Lee Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 12 +++++++++++- > 3 files changed, 13 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index 4abaa9e..07a162c 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -92,7 +92,7 @@ enum port { > }; > #define port_name(p) ((p) + 'A') > =20 > -#define I915_NUM_PHYS_VLV 1 > +#define I915_NUM_PHYS_VLV 2 > =20 > enum dpio_channel { > DPIO_CH0, > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index c7ec7d6..beb04ab 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -457,6 +457,7 @@ > #define IOSF_PORT_PUNIT 0x4 > #define IOSF_PORT_NC 0x11 > #define IOSF_PORT_DPIO 0x12 > +#define IOSF_PORT_DPIO_2 0x1a > #define IOSF_PORT_GPIO_NC 0x13 > #define IOSF_PORT_CCK 0x14 > #define IOSF_PORT_CCU 0xA9 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 9a50b64..df6732e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1367,7 +1367,17 @@ static void intel_init_dpio(struct drm_device *dev= ) > if (!IS_VALLEYVIEW(dev)) > return; > =20 > - DPIO_PHY_IOSF_PORT(DPIO_PHY0) =3D IOSF_PORT_DPIO; > + /* > + * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), > + * CHV x1 PHY (DP/HDMI D) > + * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) > + */ > + if (IS_CHERRYVIEW(dev)) { > + DPIO_PHY_IOSF_PORT(DPIO_PHY0) =3D IOSF_PORT_DPIO_2; > + DPIO_PHY_IOSF_PORT(DPIO_PHY1) =3D IOSF_PORT_DPIO; > + } else { > + DPIO_PHY_IOSF_PORT(DPIO_PHY0) =3D IOSF_PORT_DPIO; > + } > } > =20 > static void intel_reset_dpio(struct drm_device *dev) --=-rocKL0eAiiHVc0waqIzi Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTcLATAAoJEORIIAnNuWDF0XoIAO3eusBAjvIdDZuO1OqEwhYQ 8m/T7XtAyH2M773V2Ydaehrqb+bzoK3QUrNv34CPI6tfTpcSEn36vvf3HjSTs/LH QNafU7wJdysbg1BHp1WDzVavlSDgGPrRv9bPlM3DxFW2338cMETNCfgvoRYHtd4k hQkt14bdsPYaRTW0XVv3rAS0JmWilPRgH31UZaTVuAnxav4uamiIZzNnBKbuEWKV MLGsoYKUHuo2JAUp9eSnVPha8zpLqtnTvYLbvTXqmZIo66zfnw9InrS8yOO8ItVS y1A2dPdPQelsVq34dM/yZSzI79YipUpHhT90WP8giAB7p9oldXFE0SmCfr7YC1E= =9fCi -----END PGP SIGNATURE----- --=-rocKL0eAiiHVc0waqIzi-- --===============1701219643== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1701219643==--