From: "Woodruff, Richard" <r-woodruff2@ti.com>
To: Kim Kyuwon <chammoru@gmail.com>,
Kevin Hilman <khilman@deeprootsystems.com>,
OMAP <linux-omap@vger.kernel.org>,
"Nayak, Rajendra" <rnayak@ti.com>
Cc: ??? <kyungmin.park@samsung.com>, ??? <bhmin@samsung.com>,
Tony Lindgren <tony@atomide.com>
Subject: RE: 4 Problems in OMAP3430 DVFS (SmartReflex, Cpufreq)
Date: Thu, 23 Apr 2009 18:27:19 -0500 [thread overview]
Message-ID: <13B9B4C6EF24D648824FF11BE896716203825FF6F1@dlee02.ent.ti.com> (raw)
In-Reply-To: <4d34a0a70904222200oc699378k56367cf3b378b5d9@mail.gmail.com>
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Kim Kyuwon
> Sent: Thursday, April 23, 2009 12:00 AM
> 3. OP(Operating Point) transition time is set to 10seconds in
> cpu-omap.c as follows:
> The default sampling rate of CPUFreq is set to transition_latency, so
> it becomes 10 seconds! It's really too long for DVFS. I measured
> transition latency by myself using oscilloscope and it's about 150 ~
> 200m seconds. I think TI engineers may know more accurate figure. I
> wish we could update transition latency as soon as possible.
That time sounds long. What points did you measure from and what was your system speeds?
One thing to watch our for wait_clk_stable delay. PM branch needs some tweaks here. The value of 0x800 will result in a delay which can result in your display fifo under flowing. For an 800MHz Cortex a value of 0x18 will suffice. This value can be tuned to processor frequency if you like.
When SDRC is disabled just above all traffic will be pended. You want to be past this as quick as possible.
Regards,
Richard W.
prev parent reply other threads:[~2009-04-23 23:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-04-23 5:00 PM: 4 Problems in OMAP3430 DVFS (SmartReflex, Cpufreq) Kim Kyuwon
2009-04-23 8:52 ` Paul Walmsley
2009-04-23 15:39 ` Woodruff, Richard
2009-05-07 7:42 ` Kim Kyuwon
2009-04-23 23:27 ` Woodruff, Richard [this message]
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