From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexandre Courbot Subject: [PATCH 0/4] drm/ttm: nouveau: memory coherency fixes for ARM Date: Mon, 19 May 2014 16:10:54 +0900 Message-ID: <1400483458-9648-1-git-send-email-acourbot@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Nouveau" To: David Airlie , Ben Skeggs , Lucas Stach , Thierry Reding Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org This small series introduces TTM helper functions as well as Nouveau hooks that are needed to ensure buffer coherency on ARM. Most of this series is a forward-port of some patches Lucas Stach sent last year and that are also needed for Nouveau GK20A support: http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html Another patch takes care of flushing the CPU write-buffer when writing BOs through a non-BAR path. Alexandre Courbot (1): drm/nouveau: introduce CPU cache flushing macro Lucas Stach (3): drm/ttm: recognize ARM arch in ioprot handler drm/ttm: introduce dma cache sync helpers drm/nouveau: hook up cache sync functions drivers/gpu/drm/nouveau/core/os.h | 17 +++++++++++++++ drivers/gpu/drm/nouveau/nouveau_bo.c | 40 +++++++++++++++++++++++++++++++++-- drivers/gpu/drm/nouveau/nouveau_bo.h | 20 ++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_gem.c | 8 ++++++- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- drivers/gpu/drm/ttm/ttm_tt.c | 25 ++++++++++++++++++++++ include/drm/ttm/ttm_bo_driver.h | 28 ++++++++++++++++++++++++ 7 files changed, 136 insertions(+), 4 deletions(-) -- 1.9.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753062AbaESHLZ (ORCPT ); Mon, 19 May 2014 03:11:25 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:11784 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753020AbaESHLW (ORCPT ); Mon, 19 May 2014 03:11:22 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 19 May 2014 00:06:30 -0700 From: Alexandre Courbot To: David Airlie , Ben Skeggs , Lucas Stach , Thierry Reding CC: , , , , , Alexandre Courbot Subject: [PATCH 0/4] drm/ttm: nouveau: memory coherency fixes for ARM Date: Mon, 19 May 2014 16:10:54 +0900 Message-ID: <1400483458-9648-1-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.9.2 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This small series introduces TTM helper functions as well as Nouveau hooks that are needed to ensure buffer coherency on ARM. Most of this series is a forward-port of some patches Lucas Stach sent last year and that are also needed for Nouveau GK20A support: http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html Another patch takes care of flushing the CPU write-buffer when writing BOs through a non-BAR path. Alexandre Courbot (1): drm/nouveau: introduce CPU cache flushing macro Lucas Stach (3): drm/ttm: recognize ARM arch in ioprot handler drm/ttm: introduce dma cache sync helpers drm/nouveau: hook up cache sync functions drivers/gpu/drm/nouveau/core/os.h | 17 +++++++++++++++ drivers/gpu/drm/nouveau/nouveau_bo.c | 40 +++++++++++++++++++++++++++++++++-- drivers/gpu/drm/nouveau/nouveau_bo.h | 20 ++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_gem.c | 8 ++++++- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- drivers/gpu/drm/ttm/ttm_tt.c | 25 ++++++++++++++++++++++ include/drm/ttm/ttm_bo_driver.h | 28 ++++++++++++++++++++++++ 7 files changed, 136 insertions(+), 4 deletions(-) -- 1.9.2