From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: [PATCH] drm/i915: Update PSR on resume. Date: Tue, 27 May 2014 16:50:14 -0700 Message-ID: <1401234614-25220-1-git-send-email-rodrigo.vivi@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pb0-f47.google.com (mail-pb0-f47.google.com [209.85.160.47]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C4B06E4DA for ; Tue, 27 May 2014 16:49:33 -0700 (PDT) Received: by mail-pb0-f47.google.com with SMTP id rp16so10035343pbb.6 for ; Tue, 27 May 2014 16:49:32 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Some registers set during setup might not be persistent after suspend/resume. This was causing bugs for some people that was unable to get PSR entry state after resume cycle. v2: Adding some comments and better commit message explaining why this is needed. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_suspend.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 56785e8..1923708 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -288,6 +288,12 @@ static void i915_restore_display(struct drm_device *dev) I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL); } + /* Forcing a full init sequence after resume to make sure all + * registers are properly set. Some might not be persistent after + * suspend/resume cycle. */ + dev_priv->psr.setup_done = false; + intel_edp_psr_update(dev); + /* only restore FBC info on the platform that supports FBC*/ intel_disable_fbc(dev); -- 1.9.0