From: "Marc Marí" <marc.mari.barcelo@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Marc Marí" <marc.mari.barcelo@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Andreas Färber" <afaerber@suse.de>,
"Stefan Hajnoczi" <stefanha@redhat.com>
Subject: [Qemu-devel] [PATCH 2/3] x86 piix4: Correct SMBus base address
Date: Mon, 9 Jun 2014 10:55:32 +0200 [thread overview]
Message-ID: <1402304133-29620-3-git-send-email-marc.mari.barcelo@gmail.com> (raw)
In-Reply-To: <1402304133-29620-1-git-send-email-marc.mari.barcelo@gmail.com>
As defined in the PIIX4 datasheet in page 135, the base address is set
on bits [15:4]. The mask was changed to match those bits.
Datasheet: http://www.intel.com/assets/pdf/datasheet/290562.pdf
Found by Stefan Hajnoczi
Signed-off-by: Marc Marí <marc.mari.barcelo@gmail.com>
---
hw/acpi/piix4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 67dc075..5f263da 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -133,7 +133,7 @@ static void smbus_io_space_update(PIIX4PMState *s)
PCIDevice *d = PCI_DEVICE(s);
s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
- s->smb_io_base &= 0xffc0;
+ s->smb_io_base &= 0xfff0;
memory_region_transaction_begin();
memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
--
1.7.10.4
next prev parent reply other threads:[~2014-06-09 8:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-09 8:55 [Qemu-devel] [PATCH 0/3] Add PIIX4 SMBus to qtest and related changes Marc Marí
2014-06-09 8:55 ` [Qemu-devel] [PATCH 1/3] smbus: fix writes Marc Marí
2014-06-09 8:55 ` Marc Marí [this message]
2014-06-09 8:55 ` [Qemu-devel] [PATCH 3/3] qtest: Add PIIX4 SMBus support for libqos Marc Marí
2014-06-09 10:33 ` Paolo Bonzini
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