From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59947) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wu1Dv-00080K-5S for qemu-devel@nongnu.org; Mon, 09 Jun 2014 11:11:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wu1Dp-0002Pc-6Q for qemu-devel@nongnu.org; Mon, 09 Jun 2014 11:10:59 -0400 Received: from mail-qc0-x236.google.com ([2607:f8b0:400d:c01::236]:64268) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wu1Do-0002PI-LJ for qemu-devel@nongnu.org; Mon, 09 Jun 2014 11:10:52 -0400 Received: by mail-qc0-f182.google.com with SMTP id m20so796835qcx.27 for ; Mon, 09 Jun 2014 08:10:52 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 10 Jun 2014 01:04:20 +1000 Message-Id: <1402326269-8573-9-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com> References: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2 08/17] target-arm: Add SCR_EL3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 15 +++++++++++++++ target-arm/helper.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cd8c9a7..111577c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -185,6 +185,7 @@ typedef struct CPUARMState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ + uint32_t scr_el3; /* Secure configuration register. */ uint32_t ifsr_el2; /* Fault status registers. */ uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ @@ -561,6 +562,20 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_ID (1ULL << 33) #define HCR_MASK ((1ULL << 34) - 1) +#define SCR_NS (1U << 0) +#define SCR_IRQ (1U << 1) +#define SCR_FIQ (1U << 2) +#define SCR_EA (1U << 3) +#define SCR_SMD (1U << 7) +#define SCR_HCE (1U << 8) +#define SCR_SIF (1U << 9) +#define SCR_RW (1U << 10) +#define SCR_ST (1U << 11) +#define SCR_TWI (1U << 12) +#define SCR_TWE (1U << 13) +#define SCR_RES1_MASK (3U << 4) +#define SCR_MASK (0x3fff & ~SCR_RES1_MASK) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target-arm/helper.c b/target-arm/helper.c index d28951a..17cf80e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2162,6 +2162,31 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + uint32_t valid_mask = SCR_MASK; + + if (!arm_feature(env, ARM_FEATURE_EL2)) { + valid_mask &= ~SCR_HCE; + + /* On ARMv7, SMD (or SCD as it is called in v7) is only + * supported if EL2 exists. The bit is UNK/SBZP when + * EL2 is unavailable. In QEMU ARMv7, we force it to always zero + * when EL2 is unavailable. + */ + if (arm_feature(env, ARM_FEATURE_V7)) { + valid_mask &= ~SCR_SMD; + } + } + + /* Set RES1 bits. */ + value |= SCR_RES1_MASK; + + /* Clear RES0 bits. */ + value &= valid_mask; + raw_write(env, ri, value); +} + static const ARMCPRegInfo v8_el3_cp_reginfo[] = { { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, @@ -2184,6 +2209,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue = 0 }, + { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), + .writefn = scr_write }, REGINFO_SENTINEL }; -- 1.8.3.2