From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVt6-0007Sj-0N for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVt0-00049L-DS for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:31 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:2292) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVt0-00048r-3z for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:26 -0400 From: Fabian Aggeler Date: Wed, 11 Jun 2014 01:54:42 +0200 Message-ID: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v3 00/32] target-arm: add Security Extensions for CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Hi, this is round 3 of the Security Extension patches which started with the TrustZone patchset by Samsung. Many patches were dropped or got separated from this patchset. It shows yet another mechanism of register banking for EL3 running in Aarch32 mode. This version also conforms better with the ARM ARMv8. The patches got reordered with banking related patches at the end. Most of the registers get converted separately now. The whole patchset is based on master with Edgar's patches of yesterday (v2 target-arm: Parts of the Aarch64 EL2/3 exception model) applied. Patch 9,10,11 and 12 are added for some more discussion about Edgar's patches which break out masking and target_el. Parts of it could probably be added to Edgar's patchset. v2 -> v3: * rebased * reordered * changed from ARM_FEATURE_SECURITY_EXTENSIONS to ARM_FEATURE_EL3 * renamed tz_cp_reginfo to security_cp_reginfo * extended arm_is_secure() with EL3 handling * rewrote nsacr patch * removed MMU split for secure/nonsecure world * removed arm_current_sctlr * new banking scheme v2: http://lists.gnu.org/archive/html/qemu-devel/2014-05/msg02522.html Thanks, Fabian Fabian Aggeler (29): target-arm: add cpu feature EL3 to CPUs with Security Extensions target-arm: move Aarch32 SCR into security reglist target-arm: increase arrays of registers R13 & R14 target-arm: add arm_is_secure() function target-arm: make arm_current_pl() return PL3 target-arm: A32: Emulate the SMC instruction target-arm: extend Aarch32 async excp masking target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling target-arm: add async excp target_el&mode function target-arm: use dedicated target_el function target-arm: implement IRQ/FIQ routing to Monitor mode target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI target-arm: add NSACR register target-arm: add MVBAR support target-arm: add macros to access banked registers target-arm: insert Aarch32 cpregs twice into hashtable target-arm: arrayfying fieldoffset for banking target-arm: add SCTLR_EL3 and make SCTLR banked target-arm: make CSSELR banked target-arm: add TTBR0_EL3 and make TTBR0/1 banked target-arm: add TCR_EL3 and make TTBCR banked target-arm: make c2_mask and c2_base_mask banked target-arm: make DACR banked target-arm: make IFSR banked target-arm: make DFSR banked target-arm: make IFAR/DFAR banked target-arm: make PAR banked target-arm: make VBAR banked target-arm: make c13 cp regs banked (FCSEIDR,...) Sergey Fedorov (3): target-arm: reject switching to monitor mode target-arm: add non-secure Translation Block flag target-arm: add SDER definition hw/arm/pxa2xx.c | 4 +- target-arm/cpu.c | 11 +- target-arm/cpu.h | 453 +++++++++++++++++++++++++---- target-arm/helper-a64.c | 37 ++- target-arm/helper.c | 702 ++++++++++++++++++++++++++++++++++----------- target-arm/internals.h | 5 + target-arm/machine.c | 4 +- target-arm/op_helper.c | 2 +- target-arm/translate-a64.c | 1 + target-arm/translate.c | 57 ++-- target-arm/translate.h | 1 + 11 files changed, 1031 insertions(+), 246 deletions(-) -- 1.8.3.2