From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38827) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtL-0007kh-4W for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVtD-0004Gp-VA for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:47 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:14842) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtD-0004GT-Fk for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:39 -0400 From: Fabian Aggeler Date: Wed, 11 Jun 2014 01:55:06 +0200 Message-ID: <1402444514-19658-25-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v3 24/32] target-arm: add TCR_EL3 and make TTBCR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust translation functions to use TCR/TTBCR instance depending on CPU state. Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 11 ++++++++++- target-arm/helper.c | 46 ++++++++++++++++++++++++++++++++++------------ 2 files changed, 44 insertions(+), 13 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6890e82..f26baac 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -222,7 +222,16 @@ typedef struct CPUARMState { uint64_t ttbr1_el1; }; }; - uint64_t c2_control; /* MMU translation table base control. */ + union { /* MMU translation table base control. */ + struct { + uint64_t ttbcr_ns; + uint64_t ttbcr_s; + }; + struct { + uint64_t tcr_el1; + uint64_t tcr_el3; + }; + }; uint32_t c2_mask; /* MMU translation table base selection mask. */ uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ uint32_t c2_data; /* MPU data cachable bits. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 22609ed..85de791 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -312,7 +312,7 @@ static inline bool extended_addresses_enabled(CPUARMState *env) { return arm_el_is_aa64(env, 1) || ((arm_feature(env, ARM_FEATURE_LPAE) - && (env->cp15.c2_control & (1U << 31)))); + && (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & (1U << 31)))); } static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -1510,11 +1510,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .writefn = vmsa_tcr_el1_write, .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, - .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, + .fieldoffset = offsetof(CPUARMState, cp15.tcr_el1) }, { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write, .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, - .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) }, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ttbcr_s), + offsetoflow32(CPUARMState, cp15.ttbcr_ns) } }, /* 64-bit FAR; this entry also gives us the AArch32 DFAR */ { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, @@ -2278,6 +2279,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 6, .opc2 = 0, .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el3) }, + { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 6, .opc2 = 2, + .access = PL3_RW, .writefn = vmsa_tcr_el1_write, + .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.tcr_el3) }, { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, @@ -4228,13 +4234,29 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, int32_t va_size = 32; int32_t tbi = 0; uint32_t cur_el = arm_current_pl(env); + uint64_t tcr; - if (arm_el_is_aa64(env, 1)) { + if (arm_el_is_aa64(env, 3)) { + switch (cur_el) { + case 3: + tcr = env->cp15.tcr_el3; + break; + case 1: + case 0: + default: + tcr = env->cp15.tcr_el1; + } + + } else { + tcr = A32_BANKED_CURRENT_REG_GET(env, ttbcr); + } + + if (arm_el_is_aa64(env, 1) && (cur_el == 0 || cur_el == 1)) { va_size = 64; if (extract64(address, 55, 1)) - tbi = extract64(env->cp15.c2_control, 38, 1); + tbi = extract64(tcr, 38, 1); else - tbi = extract64(env->cp15.c2_control, 37, 1); + tbi = extract64(tcr, 37, 1); tbi *= 8; } @@ -4243,12 +4265,12 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, * This is a Non-secure PL0/1 stage 1 translation, so controlled by * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: */ - uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6); + uint32_t t0sz = extract32(tcr, 0, 6); if (arm_el_is_aa64(env, 1)) { t0sz = MIN(t0sz, 39); t0sz = MAX(t0sz, 16); } - uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6); + uint32_t t1sz = extract32(tcr, 16, 6); if (arm_el_is_aa64(env, 1)) { t1sz = MIN(t1sz, 39); t1sz = MAX(t1sz, 16); @@ -4292,10 +4314,10 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, } else { ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0); } - epd = extract32(env->cp15.c2_control, 7, 1); + epd = extract32(tcr, 7, 1); tsz = t0sz; - tg = extract32(env->cp15.c2_control, 14, 2); + tg = extract32(tcr, 14, 2); if (tg == 1) { /* 64KB pages */ granule_sz = 13; } @@ -4304,10 +4326,10 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, } } else { ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1); - epd = extract32(env->cp15.c2_control, 23, 1); + epd = extract32(tcr, 23, 1); tsz = t1sz; - tg = extract32(env->cp15.c2_control, 30, 2); + tg = extract32(tcr, 30, 2); if (tg == 3) { /* 64KB pages */ granule_sz = 13; } -- 1.8.3.2