From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38858) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtM-0007nG-GN for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVtE-0004HP-H7 for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:48 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:2331) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtE-0004Gh-6E for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:40 -0400 From: Fabian Aggeler Date: Wed, 11 Jun 2014 01:55:07 +0200 Message-ID: <1402444514-19658-26-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v3 25/32] target-arm: make c2_mask and c2_base_mask banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This avoids recalculating them on switches from secure to non-secure world. Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 10 ++++++++-- target-arm/helper.c | 19 ++++++++++++------- 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f26baac..09f658b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -232,8 +232,14 @@ typedef struct CPUARMState { uint64_t tcr_el3; }; }; - uint32_t c2_mask; /* MMU translation table base selection mask. */ - uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ + struct { /* MMU translation table base selection mask. */ + uint32_t c2_mask_ns; + uint32_t c2_mask_s; + }; + struct { /* MMU translation table base 0 mask. */ + uint32_t c2_base_mask_ns; + uint32_t c2_base_mask_s; + }; uint32_t c2_data; /* MPU data cachable bits. */ uint32_t c2_insn; /* MPU instruction cachable bits. */ uint32_t c3; /* MMU domain access control register diff --git a/target-arm/helper.c b/target-arm/helper.c index 85de791..2c48895 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1435,8 +1435,11 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, * and the c2_mask and c2_base_mask values are meaningless. */ raw_write(env, ri, value); - env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); - env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); + + A32_BANKED_CURRENT_REG_SET(env, c2_mask, + ~(((uint32_t)0xffffffffu) >> maskshift)); + A32_BANKED_CURRENT_REG_SET(env, c2_base_mask, + ~((uint32_t)0x3fffu >> maskshift)); } static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1455,9 +1458,9 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) { - env->cp15.c2_base_mask = 0xffffc000u; + A32_BANKED_CURRENT_REG_SET(env, c2_base_mask, 0xffffc000u); raw_write(env, ri, 0); - env->cp15.c2_mask = 0; + A32_BANKED_CURRENT_REG_SET(env, c2_mask, 0); } static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3984,10 +3987,12 @@ static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address) * Aarch32 there is a secure and non-secure instance of the translation * table registers. */ - if (address & env->cp15.c2_mask) + if (address & A32_BANKED_CURRENT_REG_GET(env, c2_mask)) { table = A32_BANKED_CURRENT_REG_GET(env, ttbr1) & 0xffffc000; - else - table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) & env->cp15.c2_base_mask; + } else { + table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) & + A32_BANKED_CURRENT_REG_GET(env, c2_base_mask); + } table |= (address >> 18) & 0x3ffc; return table; -- 1.8.3.2