From mboxrd@z Thu Jan 1 00:00:00 1970 From: vijay.kilari@gmail.com Subject: [PATCH v5 20/21] xen/arm: add SGI handling for GICv3 Date: Thu, 12 Jun 2014 19:06:31 +0530 Message-ID: <1402580192-13937-21-git-send-email-vijay.kilari@gmail.com> References: <1402580192-13937-1-git-send-email-vijay.kilari@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1402580192-13937-1-git-send-email-vijay.kilari@gmail.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian.Campbell@citrix.com, julien.grall@linaro.org, stefano.stabellini@eu.citrix.com, stefano.stabellini@citrix.com, tim@xen.org, xen-devel@lists.xen.org Cc: Prasun.Kapoor@caviumnetworks.com, Vijaya Kumar K , vijay.kilari@gmail.com List-Id: xen-devel@lists.xenproject.org From: Vijaya Kumar K In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2. Handle the trap and inject SGI to vcpu. Signed-off-by: Vijaya Kumar K --- xen/arch/arm/traps.c | 30 ++++++++++++++++++++ xen/arch/arm/vgic-v3.c | 55 +++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/gic_v3_defs.h | 7 +++++ xen/include/asm-arm/sysregs.h | 3 ++ xen/include/asm-arm/vgic.h | 1 + 5 files changed, 96 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 9348147..1ac01ee 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -41,6 +41,7 @@ #include "decode.h" #include "vtimer.h" #include +#include /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in @@ -496,6 +497,18 @@ static void inject_dabt_exception(struct cpu_user_regs *regs, #endif } +static void inject_undef_exception(struct cpu_user_regs *regs, + register_t addr, + int instr_len) +{ + if ( is_32bit_domain(current->domain) ) + inject_undef32_exception(regs); +#ifdef CONFIG_ARM_64 + else + inject_undef64_exception(regs, instr_len); +#endif +} + struct reg_ctxt { /* Guest-side state */ uint32_t sctlr_el1; @@ -1467,6 +1480,7 @@ static void do_sysreg(struct cpu_user_regs *regs, union hsr hsr) { register_t *x = select_user_reg(regs, hsr.sysreg.reg); + register_t addr; switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) { @@ -1515,6 +1529,22 @@ static void do_sysreg(struct cpu_user_regs *regs, domain_crash_synchronous(); } break; + case HSR_SYSREG_ICC_SGI1R_EL1: + if ( !vgic_emulate(regs, hsr) ) + { + addr = READ_SYSREG64(FAR_EL2); + dprintk(XENLOG_WARNING, + "failed emulation of sysreg ICC_SGI1R_EL1 access\n"); + inject_undef_exception(regs, addr, hsr.len); + } + break; + case HSR_SYSREG_ICC_SGI0R_EL1: + case HSR_SYSREG_ICC_ASGI1R_EL1: + /* TBD: Implement to support secure grp0/1 SGI forwarding */ + dprintk(XENLOG_WARNING, + "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not supported\n"); + addr = READ_SYSREG64(FAR_EL2); + inject_undef_exception(regs, addr, hsr.len); default: bad_sysreg: { diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index b116d27..45bb090 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -34,6 +34,10 @@ #include #include +extern int vgic_to_sgi(struct vcpu *v, register_t sgir, + enum gic_sgi_mode irqmode, int virq, + unsigned long vcpu_mask); + static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, uint32_t gicr_reg) { @@ -837,6 +841,57 @@ write_ignore_64: return 1; } +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir) +{ + int virq; + int irqmode; + enum gic_sgi_mode sgi_mode; + unsigned long vcpu_mask = 0; + + irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK; + virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK; + vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK; + + /* Map GIC sgi value to enum value */ + switch ( irqmode ) + { + case ICH_SGI_TARGET_LIST: + sgi_mode = SGI_TARGET_LIST; + break; + case ICH_SGI_TARGET_OTHERS: + sgi_mode = SGI_TARGET_OTHERS; + break; + default: + BUG(); + } + + return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask); +} + +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr) +{ + struct vcpu *v = current; + struct hsr_sysreg sysreg = hsr.sysreg; + register_t *r = select_user_reg(regs, sysreg.reg); + + ASSERT (hsr.ec == HSR_EC_SYSREG); + + switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) + { + case HSR_SYSREG_ICC_SGI1R_EL1: + /* WO */ + if ( !sysreg.read ) + return vgicv3_to_sgi(v, *r); + else + { + gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n"); + return 0; + } + default: + return 0; + } +} + static const struct mmio_handler_ops vgic_rdistr_mmio_handler = { .read_handler = vgic_v3_rdistr_mmio_read, .write_handler = vgic_v3_rdistr_mmio_write, diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index b8d2e77..ce7e6b3 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -145,6 +145,13 @@ #define GICH_VMCR_PRIORITY_MASK 0xff #define GICH_VMCR_PRIORITY_SHIFT 24 +#define ICH_SGI_IRQMODE_SHIFT 40 +#define ICH_SGI_IRQMODE_MASK 0x1 +#define ICH_SGI_TARGET_OTHERS 1 +#define ICH_SGI_TARGET_LIST 0 +#define ICH_SGI_IRQ_SHIFT 24 +#define ICH_SGI_IRQ_MASK 0xf +#define ICH_SGI_TARGETLIST_MASK 0xffff #endif /* __ASM_ARM_GIC_V3_DEFS_H__ */ /* diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h index 4a4de34..5029851 100644 --- a/xen/include/asm-arm/sysregs.h +++ b/xen/include/asm-arm/sysregs.h @@ -77,6 +77,9 @@ #define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2) #define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0) #define HSR_SYSREG_AMAIR_EL1 HSR_SYSREG(3,0,c10,c3,0) +#define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5) +#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6) +#define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7) #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1) #define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index a237f4d..0fa4d86 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -163,6 +163,7 @@ extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq); extern void vgic_clear_pending_irqs(struct vcpu *v); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); extern struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n, int s); +extern int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr); extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n); extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n); extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops); -- 1.7.9.5