[PATCH 1/4] of: Add vendor prefix for Chips&Media, Inc.

[PATCH 1/4] of: Add vendor prefix for Chips&Media, Inc.

[Philipp Zabel]

Chips&Media is a developer of Video Codec IP cores.

Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index abc3080..a628127 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -29,6 +29,7 @@ cavium	Cavium, Inc.
 cdns	Cadence Design Systems Inc.
 chrp	Common Hardware Reference Platform
 chunghwa	Chunghwa Picture Tubes Ltd.
+cnm	Chips&Media, Inc.
 cirrus	Cirrus Logic, Inc.
 cortina	Cortina Systems, Inc.
 crystalfontz	Crystalfontz America, Inc.
-- 
2.0.0

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[PATCH 1/4] of: Add vendor prefix for Chips&Media, Inc.

[Philipp Zabel]

Chips&Media is a developer of Video Codec IP cores.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index abc3080..a628127 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -29,6 +29,7 @@ cavium	Cavium, Inc.
 cdns	Cadence Design Systems Inc.
 chrp	Common Hardware Reference Platform
 chunghwa	Chunghwa Picture Tubes Ltd.
+cnm	Chips&Media, Inc.
 cirrus	Cirrus Logic, Inc.
 cortina	Cortina Systems, Inc.
 crystalfontz	Crystalfontz America, Inc.
-- 
2.0.0

[PATCH 2/4] of: Add new compatibles for CODA bindings

[Philipp Zabel]

This patch adds new compatibles using the new Chips&Media vendor
prefix "cnm" and CODA model name as well as a Freescale specific
compatible value for i.MX6DL/S.
The latter is because for some reason the i.MX6DL/S firmware
provided by Freescale differs from the i.MX6Q/D version.

Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 Documentation/devicetree/bindings/media/coda.txt | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/coda.txt b/Documentation/devicetree/bindings/media/coda.txt
index 2865d04..f5e4d4b 100644
--- a/Documentation/devicetree/bindings/media/coda.txt
+++ b/Documentation/devicetree/bindings/media/coda.txt
@@ -5,10 +5,11 @@ Coda codec IPs are present in i.MX SoCs in various versions,
 called VPU (Video Processing Unit).
 
 Required properties:
-- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
-  (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
-  (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53
-  (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
+- compatible : should be "fsl,<chip>-src", "cnm,coda<model>" for i.MX SoCs:
+  (a) "fsl,imx27-vpu", "cnm,codadx6" for CodaDx6 present in i.MX27
+  (b) "fsl,imx53-vpu", "cnm,coda7541" for CODA7541 present in i.MX53
+  (c) "fsl,imx6q-vpu", "cnm,coda960" for CODA960 present in i.MX6Q/D
+  (d) "fsl,imx6dl-vpu", "cnm,coda960" for CODA960 present in i.MX6DL/S
 - reg: should be register base and length as documented in the
   SoC reference manual
 - interrupts : Should contain the VPU interrupt. For CODA960,
@@ -21,7 +22,7 @@ Required properties:
 Example:
 
 vpu: vpu@63ff4000 {
-	compatible = "fsl,imx53-vpu";
+	compatible = "fsl,imx53-vpu", "cnm,coda7541";
 	reg = <0x63ff4000 0x1000>;
 	interrupts = <9>;
 	clocks = <&clks 63>, <&clks 63>;
-- 
2.0.0

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[PATCH 2/4] of: Add new compatibles for CODA bindings

[Philipp Zabel]

This patch adds new compatibles using the new Chips&Media vendor
prefix "cnm" and CODA model name as well as a Freescale specific
compatible value for i.MX6DL/S.
The latter is because for some reason the i.MX6DL/S firmware
provided by Freescale differs from the i.MX6Q/D version.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 Documentation/devicetree/bindings/media/coda.txt | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/coda.txt b/Documentation/devicetree/bindings/media/coda.txt
index 2865d04..f5e4d4b 100644
--- a/Documentation/devicetree/bindings/media/coda.txt
+++ b/Documentation/devicetree/bindings/media/coda.txt
@@ -5,10 +5,11 @@ Coda codec IPs are present in i.MX SoCs in various versions,
 called VPU (Video Processing Unit).
 
 Required properties:
-- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
-  (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
-  (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53
-  (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
+- compatible : should be "fsl,<chip>-src", "cnm,coda<model>" for i.MX SoCs:
+  (a) "fsl,imx27-vpu", "cnm,codadx6" for CodaDx6 present in i.MX27
+  (b) "fsl,imx53-vpu", "cnm,coda7541" for CODA7541 present in i.MX53
+  (c) "fsl,imx6q-vpu", "cnm,coda960" for CODA960 present in i.MX6Q/D
+  (d) "fsl,imx6dl-vpu", "cnm,coda960" for CODA960 present in i.MX6DL/S
 - reg: should be register base and length as documented in the
   SoC reference manual
 - interrupts : Should contain the VPU interrupt. For CODA960,
@@ -21,7 +22,7 @@ Required properties:
 Example:
 
 vpu: vpu at 63ff4000 {
-	compatible = "fsl,imx53-vpu";
+	compatible = "fsl,imx53-vpu", "cnm,coda7541";
 	reg = <0x63ff4000 0x1000>;
 	interrupts = <9>;
 	clocks = <&clks 63>, <&clks 63>;
-- 
2.0.0

[PATCH 3/4] of: Add named interrupts to CODA bindings

[Philipp Zabel]

This patch documents named interrupt bindings for the CODA
video processing units.

Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 Documentation/devicetree/bindings/media/coda.txt | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/coda.txt b/Documentation/devicetree/bindings/media/coda.txt
index f5e4d4b..a44c4aa 100644
--- a/Documentation/devicetree/bindings/media/coda.txt
+++ b/Documentation/devicetree/bindings/media/coda.txt
@@ -12,19 +12,24 @@ Required properties:
   (d) "fsl,imx6dl-vpu", "cnm,coda960" for CODA960 present in i.MX6DL/S
 - reg: should be register base and length as documented in the
   SoC reference manual
-- interrupts : Should contain the VPU interrupt. For CODA960,
-  a second interrupt is needed for the MJPEG unit.
+- interrupts : Should contain the VPU (BIT processor) interrupt.
+  For CODA960, a second interrupt is needed for the JPEG unit.
 - clocks : Should contain the ahb and per clocks, in the order
   determined by the clock-names property.
 - clock-names : Should be "ahb", "per"
 - iram : phandle pointing to the SRAM device node
 
+Optional properties:
+- interrupt-names: Should be "bit" for the BIT processor interrupt
+  and "jpeg" for the JPEG unit interrupt on CODA960.
+
 Example:
 
 vpu: vpu@63ff4000 {
 	compatible = "fsl,imx53-vpu", "cnm,coda7541";
 	reg = <0x63ff4000 0x1000>;
 	interrupts = <9>;
+	interrupt-names = "bit";
 	clocks = <&clks 63>, <&clks 63>;
 	clock-names = "ahb", "per";
 	iram = <&ocram>;
-- 
2.0.0

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[PATCH 3/4] of: Add named interrupts to CODA bindings

[Philipp Zabel]

This patch documents named interrupt bindings for the CODA
video processing units.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 Documentation/devicetree/bindings/media/coda.txt | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/coda.txt b/Documentation/devicetree/bindings/media/coda.txt
index f5e4d4b..a44c4aa 100644
--- a/Documentation/devicetree/bindings/media/coda.txt
+++ b/Documentation/devicetree/bindings/media/coda.txt
@@ -12,19 +12,24 @@ Required properties:
   (d) "fsl,imx6dl-vpu", "cnm,coda960" for CODA960 present in i.MX6DL/S
 - reg: should be register base and length as documented in the
   SoC reference manual
-- interrupts : Should contain the VPU interrupt. For CODA960,
-  a second interrupt is needed for the MJPEG unit.
+- interrupts : Should contain the VPU (BIT processor) interrupt.
+  For CODA960, a second interrupt is needed for the JPEG unit.
 - clocks : Should contain the ahb and per clocks, in the order
   determined by the clock-names property.
 - clock-names : Should be "ahb", "per"
 - iram : phandle pointing to the SRAM device node
 
+Optional properties:
+- interrupt-names: Should be "bit" for the BIT processor interrupt
+  and "jpeg" for the JPEG unit interrupt on CODA960.
+
 Example:
 
 vpu: vpu at 63ff4000 {
 	compatible = "fsl,imx53-vpu", "cnm,coda7541";
 	reg = <0x63ff4000 0x1000>;
 	interrupts = <9>;
+	interrupt-names = "bit";
 	clocks = <&clks 63>, <&clks 63>;
 	clock-names = "ahb", "per";
 	iram = <&ocram>;
-- 
2.0.0

[PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Philipp Zabel]

This patch adds links to the on-chip SRAM and reset controller nodes
and switches the interrupts. Make the BIT processor interrupt, which exists on
all variants, the first one. The JPEG unit interrupt, which does not exist on
i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
load separate firmware images for some reason.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
 arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
 arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5c5f574..fbbdfca 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -110,3 +110,7 @@
 		      "di0_sel", "di1_sel",
 		      "di0", "di1";
 };
+
+&vpu {
+	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index addd3f8..2c1dbf8 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -291,3 +291,7 @@
 		};
 	};
 };
+
+&vpu {
+	compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index eca0971..2052303 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -315,9 +315,15 @@
 			};
 
 			vpu: vpu@02040000 {
+				compatible = "cnm,coda960";
 				reg = <0x02040000 0x3c000>;
-				interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
-				             <0 12 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+				             <0 3 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "bit", "jpeg";
+				clocks = <&clks 168>, <&clks 168>;
+				clock-names = "per", "ahb";
+				resets = <&src 1>;
+				iram = <&ocram>;
 			};
 
 			aipstz@0207c000 { /* AIPSTZ1 */
-- 
2.0.0

[PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Philipp Zabel]

This patch adds links to the on-chip SRAM and reset controller nodes
and switches the interrupts. Make the BIT processor interrupt, which exists on
all variants, the first one. The JPEG unit interrupt, which does not exist on
i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
load separate firmware images for some reason.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
 arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
 arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5c5f574..fbbdfca 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -110,3 +110,7 @@
 		      "di0_sel", "di1_sel",
 		      "di0", "di1";
 };
+
+&vpu {
+	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index addd3f8..2c1dbf8 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -291,3 +291,7 @@
 		};
 	};
 };
+
+&vpu {
+	compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index eca0971..2052303 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -315,9 +315,15 @@
 			};
 
 			vpu: vpu at 02040000 {
+				compatible = "cnm,coda960";
 				reg = <0x02040000 0x3c000>;
-				interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
-				             <0 12 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+				             <0 3 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "bit", "jpeg";
+				clocks = <&clks 168>, <&clks 168>;
+				clock-names = "per", "ahb";
+				resets = <&src 1>;
+				iram = <&ocram>;
 			};
 
 			aipstz at 0207c000 { /* AIPSTZ1 */
-- 
2.0.0

Re: [PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Rob Herring]

On Fri, Jun 13, 2014 at 12:14 PM, Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> This patch adds links to the on-chip SRAM and reset controller nodes
> and switches the interrupts. Make the BIT processor interrupt, which exists on
> all variants, the first one. The JPEG unit interrupt, which does not exist on
> i.MX27 and i.MX5 thus is an optional second interrupt.
> Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
> load separate firmware images for some reason.
>
> Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
>  arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
>  arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
>  arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
>  3 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 5c5f574..fbbdfca 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -110,3 +110,7 @@
>                       "di0_sel", "di1_sel",
>                       "di0", "di1";
>  };
> +
> +&vpu {
> +       compatible = "fsl,imx6dl-vpu", "cnm,coda960";
> +};
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index addd3f8..2c1dbf8 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -291,3 +291,7 @@
>                 };
>         };
>  };
> +
> +&vpu {
> +       compatible = "fsl,imx6q-vpu", "cnm,coda960";
> +};
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index eca0971..2052303 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -315,9 +315,15 @@
>                         };
>
>                         vpu: vpu@02040000 {
> +                               compatible = "cnm,coda960";
>                                 reg = <0x02040000 0x3c000>;
> -                               interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
> -                                            <0 12 IRQ_TYPE_LEVEL_HIGH>;
> +                               interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
> +                                            <0 3 IRQ_TYPE_LEVEL_HIGH>;

Is there an existing user? This would break things if so.

Rob
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[PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Rob Herring]

On Fri, Jun 13, 2014 at 12:14 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> This patch adds links to the on-chip SRAM and reset controller nodes
> and switches the interrupts. Make the BIT processor interrupt, which exists on
> all variants, the first one. The JPEG unit interrupt, which does not exist on
> i.MX27 and i.MX5 thus is an optional second interrupt.
> Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
> load separate firmware images for some reason.
>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
>  arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
>  arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
>  arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
>  3 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 5c5f574..fbbdfca 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -110,3 +110,7 @@
>                       "di0_sel", "di1_sel",
>                       "di0", "di1";
>  };
> +
> +&vpu {
> +       compatible = "fsl,imx6dl-vpu", "cnm,coda960";
> +};
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index addd3f8..2c1dbf8 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -291,3 +291,7 @@
>                 };
>         };
>  };
> +
> +&vpu {
> +       compatible = "fsl,imx6q-vpu", "cnm,coda960";
> +};
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index eca0971..2052303 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -315,9 +315,15 @@
>                         };
>
>                         vpu: vpu at 02040000 {
> +                               compatible = "cnm,coda960";
>                                 reg = <0x02040000 0x3c000>;
> -                               interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
> -                                            <0 12 IRQ_TYPE_LEVEL_HIGH>;
> +                               interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
> +                                            <0 3 IRQ_TYPE_LEVEL_HIGH>;

Is there an existing user? This would break things if so.

Rob

Re: [PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Philipp Zabel]

On Fri, Jun 13, 2014 at 03:46:43PM -0500, Rob Herring wrote:
> On Fri, Jun 13, 2014 at 12:14 PM, Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> > This patch adds links to the on-chip SRAM and reset controller nodes
> > and switches the interrupts. Make the BIT processor interrupt, which exists on
> > all variants, the first one. The JPEG unit interrupt, which does not exist on
> > i.MX27 and i.MX5 thus is an optional second interrupt.
> > Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
> > load separate firmware images for some reason.
> >
> > Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > ---
> >  arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
> >  arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
> >  arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
> >  3 files changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> > index 5c5f574..fbbdfca 100644
> > --- a/arch/arm/boot/dts/imx6dl.dtsi
> > +++ b/arch/arm/boot/dts/imx6dl.dtsi
> > @@ -110,3 +110,7 @@
> >                       "di0_sel", "di1_sel",
> >                       "di0", "di1";
> >  };
> > +
> > +&vpu {
> > +       compatible = "fsl,imx6dl-vpu", "cnm,coda960";
> > +};
> > diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> > index addd3f8..2c1dbf8 100644
> > --- a/arch/arm/boot/dts/imx6q.dtsi
> > +++ b/arch/arm/boot/dts/imx6q.dtsi
> > @@ -291,3 +291,7 @@
> >                 };
> >         };
> >  };
> > +
> > +&vpu {
> > +       compatible = "fsl,imx6q-vpu", "cnm,coda960";
> > +};
> > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> > index eca0971..2052303 100644
> > --- a/arch/arm/boot/dts/imx6qdl.dtsi
> > +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> > @@ -315,9 +315,15 @@
> >                         };
> >
> >                         vpu: vpu@02040000 {
> > +                               compatible = "cnm,coda960";
> >                                 reg = <0x02040000 0x3c000>;
> > -                               interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
> > -                                            <0 12 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
> > +                                            <0 3 IRQ_TYPE_LEVEL_HIGH>;
> 
> Is there an existing user? This would break things if so.

Not that I know of, there wasn't even a compatible value in this node.

There is an existing driver for coda7 that expects the first interrupt to be
the BIT processor interrupt (<0 12 ...> in this case). Today I have submitted
patches to linux-media that add support for coda9, which only works with this
change.

regards
Philipp
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[PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Philipp Zabel]

On Fri, Jun 13, 2014 at 03:46:43PM -0500, Rob Herring wrote:
> On Fri, Jun 13, 2014 at 12:14 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> > This patch adds links to the on-chip SRAM and reset controller nodes
> > and switches the interrupts. Make the BIT processor interrupt, which exists on
> > all variants, the first one. The JPEG unit interrupt, which does not exist on
> > i.MX27 and i.MX5 thus is an optional second interrupt.
> > Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
> > load separate firmware images for some reason.
> >
> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> > ---
> >  arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
> >  arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
> >  arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
> >  3 files changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> > index 5c5f574..fbbdfca 100644
> > --- a/arch/arm/boot/dts/imx6dl.dtsi
> > +++ b/arch/arm/boot/dts/imx6dl.dtsi
> > @@ -110,3 +110,7 @@
> >                       "di0_sel", "di1_sel",
> >                       "di0", "di1";
> >  };
> > +
> > +&vpu {
> > +       compatible = "fsl,imx6dl-vpu", "cnm,coda960";
> > +};
> > diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> > index addd3f8..2c1dbf8 100644
> > --- a/arch/arm/boot/dts/imx6q.dtsi
> > +++ b/arch/arm/boot/dts/imx6q.dtsi
> > @@ -291,3 +291,7 @@
> >                 };
> >         };
> >  };
> > +
> > +&vpu {
> > +       compatible = "fsl,imx6q-vpu", "cnm,coda960";
> > +};
> > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> > index eca0971..2052303 100644
> > --- a/arch/arm/boot/dts/imx6qdl.dtsi
> > +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> > @@ -315,9 +315,15 @@
> >                         };
> >
> >                         vpu: vpu at 02040000 {
> > +                               compatible = "cnm,coda960";
> >                                 reg = <0x02040000 0x3c000>;
> > -                               interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
> > -                                            <0 12 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
> > +                                            <0 3 IRQ_TYPE_LEVEL_HIGH>;
> 
> Is there an existing user? This would break things if so.

Not that I know of, there wasn't even a compatible value in this node.

There is an existing driver for coda7 that expects the first interrupt to be
the BIT processor interrupt (<0 12 ...> in this case). Today I have submitted
patches to linux-media that add support for coda9, which only works with this
change.

regards
Philipp

Re: [PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Shawn Guo]

On Fri, Jun 13, 2014 at 07:14:01PM +0200, Philipp Zabel wrote:
> This patch adds links to the on-chip SRAM and reset controller nodes
> and switches the interrupts. Make the BIT processor interrupt, which exists on
> all variants, the first one. The JPEG unit interrupt, which does not exist on
> i.MX27 and i.MX5 thus is an optional second interrupt.
> Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
> load separate firmware images for some reason.
> 
> Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>

The whole series looks good to me.

Rob,

Do you want to apply the first patch through DT tree, or may I have your
ACK to take the whole series via IMX tree?

Shawn

> ---
>  arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
>  arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
>  arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
>  3 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 5c5f574..fbbdfca 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -110,3 +110,7 @@
>  		      "di0_sel", "di1_sel",
>  		      "di0", "di1";
>  };
> +
> +&vpu {
> +	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
> +};
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index addd3f8..2c1dbf8 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -291,3 +291,7 @@
>  		};
>  	};
>  };
> +
> +&vpu {
> +	compatible = "fsl,imx6q-vpu", "cnm,coda960";
> +};
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index eca0971..2052303 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -315,9 +315,15 @@
>  			};
>  
>  			vpu: vpu@02040000 {
> +				compatible = "cnm,coda960";
>  				reg = <0x02040000 0x3c000>;
> -				interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
> -				             <0 12 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
> +				             <0 3 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "bit", "jpeg";
> +				clocks = <&clks 168>, <&clks 168>;
> +				clock-names = "per", "ahb";
> +				resets = <&src 1>;
> +				iram = <&ocram>;
>  			};
>  
>  			aipstz@0207c000 { /* AIPSTZ1 */
> -- 
> 2.0.0
> 
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[PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Shawn Guo]

On Fri, Jun 13, 2014 at 07:14:01PM +0200, Philipp Zabel wrote:
> This patch adds links to the on-chip SRAM and reset controller nodes
> and switches the interrupts. Make the BIT processor interrupt, which exists on
> all variants, the first one. The JPEG unit interrupt, which does not exist on
> i.MX27 and i.MX5 thus is an optional second interrupt.
> Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
> load separate firmware images for some reason.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

The whole series looks good to me.

Rob,

Do you want to apply the first patch through DT tree, or may I have your
ACK to take the whole series via IMX tree?

Shawn

> ---
>  arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
>  arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
>  arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
>  3 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 5c5f574..fbbdfca 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -110,3 +110,7 @@
>  		      "di0_sel", "di1_sel",
>  		      "di0", "di1";
>  };
> +
> +&vpu {
> +	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
> +};
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index addd3f8..2c1dbf8 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -291,3 +291,7 @@
>  		};
>  	};
>  };
> +
> +&vpu {
> +	compatible = "fsl,imx6q-vpu", "cnm,coda960";
> +};
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index eca0971..2052303 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -315,9 +315,15 @@
>  			};
>  
>  			vpu: vpu at 02040000 {
> +				compatible = "cnm,coda960";
>  				reg = <0x02040000 0x3c000>;
> -				interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
> -				             <0 12 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
> +				             <0 3 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "bit", "jpeg";
> +				clocks = <&clks 168>, <&clks 168>;
> +				clock-names = "per", "ahb";
> +				resets = <&src 1>;
> +				iram = <&ocram>;
>  			};
>  
>  			aipstz at 0207c000 { /* AIPSTZ1 */
> -- 
> 2.0.0
> 

Re: [PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Philipp Zabel]

Am Mittwoch, den 18.06.2014, 23:12 +0800 schrieb Shawn Guo:
> On Fri, Jun 13, 2014 at 07:14:01PM +0200, Philipp Zabel wrote:
> > This patch adds links to the on-chip SRAM and reset controller nodes
> > and switches the interrupts. Make the BIT processor interrupt, which exists on
> > all variants, the first one. The JPEG unit interrupt, which does not exist on
> > i.MX27 and i.MX5 thus is an optional second interrupt.
> > Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
> > load separate firmware images for some reason.
> > 
> > Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> 
> The whole series looks good to me.
> 
> Rob,
> 
> Do you want to apply the first patch through DT tree, or may I have your
> ACK to take the whole series via IMX tree?

Hi,

are there any reservations about these patches being merged through
Shawn's IMX tree?

regards
Philipp

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[PATCH 4/4] ARM: dts: imx6qdl: Enable CODA960 VPU

[Philipp Zabel]

Am Mittwoch, den 18.06.2014, 23:12 +0800 schrieb Shawn Guo:
> On Fri, Jun 13, 2014 at 07:14:01PM +0200, Philipp Zabel wrote:
> > This patch adds links to the on-chip SRAM and reset controller nodes
> > and switches the interrupts. Make the BIT processor interrupt, which exists on
> > all variants, the first one. The JPEG unit interrupt, which does not exist on
> > i.MX27 and i.MX5 thus is an optional second interrupt.
> > Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
> > load separate firmware images for some reason.
> > 
> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> 
> The whole series looks good to me.
> 
> Rob,
> 
> Do you want to apply the first patch through DT tree, or may I have your
> ACK to take the whole series via IMX tree?

Hi,

are there any reservations about these patches being merged through
Shawn's IMX tree?

regards
Philipp

Re: [PATCH 1/4] of: Add vendor prefix for Chips&Media, Inc.

[Fabio Estevam]

Hi Philipp,

On Fri, Jun 13, 2014 at 2:13 PM, Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> Chips&Media is a developer of Video Codec IP cores.
>
> Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>

4/4 is in Shawn's tree now. Could you please resend patches 1,2 and 3?

Thanks
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[PATCH 1/4] of: Add vendor prefix for Chips&Media, Inc.

[Fabio Estevam]

Hi Philipp,

On Fri, Jun 13, 2014 at 2:13 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> Chips&Media is a developer of Video Codec IP cores.
>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

4/4 is in Shawn's tree now. Could you please resend patches 1,2 and 3?

Thanks