From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Stabellini Subject: [PATCH] xen/arm: introduce platform_need_explicit_eoi Date: Fri, 20 Jun 2014 14:35:16 +0100 Message-ID: <1403271316-21635-1-git-send-email-stefano.stabellini@eu.citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xensource.com Cc: apatel@apm.com, Ian.Campbell@citrix.com, psawargaonkar@apm.com, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org GICH_LR_HW doesn't work as expected on X-Gene: request maintenance interrupts and perform EOIs in the hypervisor as a workaround. Trigger this behaviour with a per platform option. No need to find the pcpu that needs to write to GICC_DIR, because after "physical irq follow virtual irq" we always inject the virtual irq on the vcpu that is running on the pcpu that received the interrupt. Signed-off-by: Stefano Stabellini CC: psawargaonkar@apm.com CC: apatel@apm.com --- xen/arch/arm/gic.c | 13 ++++++++++++- xen/arch/arm/platforms/xgene-storm.c | 2 +- xen/include/asm-arm/platform.h | 5 +++++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 58233cc..8695078 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -577,7 +577,9 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, lr_val = state | (GIC_PRI_TO_GUEST(p->priority) << GICH_LR_PRIORITY_SHIFT) | ((p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT); - if ( p->desc != NULL ) + if ( platform_has_quirk(PLATFORM_QUIRK_NEED_EOI) ) + lr_val |= GICH_LR_MAINTENANCE_IRQ; + else if ( p->desc != NULL ) lr_val |= GICH_LR_HW | (p->desc->irq << GICH_LR_PHYSICAL_SHIFT); GICH[GICH_LR + lr] = lr_val; @@ -656,6 +658,11 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, gic_add_to_lr_pending(v, irq_to_pending(v, virtual_irq)); } +static void gic_irq_eoi(int irq) +{ + GICC[GICC_DIR] = irq; +} + static void gic_update_one_lr(struct vcpu *v, int i) { struct pending_irq *p; @@ -692,7 +699,11 @@ static void gic_update_one_lr(struct vcpu *v, int i) clear_bit(i, &this_cpu(lr_mask)); if ( p->desc != NULL ) + { p->desc->status &= ~IRQ_INPROGRESS; + if ( platform_has_quirk(PLATFORM_QUIRK_NEED_EOI) ) + gic_irq_eoi(p->irq); + } clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); clear_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); p->lr = GIC_INVALID_LR; diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c index c9dd63c..5396c46 100644 --- a/xen/arch/arm/platforms/xgene-storm.c +++ b/xen/arch/arm/platforms/xgene-storm.c @@ -37,7 +37,7 @@ static bool reset_vals_valid = false; static uint32_t xgene_storm_quirks(void) { - return PLATFORM_QUIRK_GIC_64K_STRIDE; + return PLATFORM_QUIRK_GIC_64K_STRIDE|PLATFORM_QUIRK_NEED_EOI; } static int map_one_mmio(struct domain *d, const char *what, diff --git a/xen/include/asm-arm/platform.h b/xen/include/asm-arm/platform.h index bcd2097..572f5b1 100644 --- a/xen/include/asm-arm/platform.h +++ b/xen/include/asm-arm/platform.h @@ -55,6 +55,11 @@ struct platform_desc { */ #define PLATFORM_QUIRK_GIC_64K_STRIDE (1 << 0) +/* + * Quirk for platforms where GICH_LR_HW does not work as expected. + */ +#define PLATFORM_QUIRK_NEED_EOI (1 << 1) + void __init platform_init(void); int __init platform_init_time(void); int __init platform_specific_mapping(struct domain *d); -- 1.7.10.4