From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WyKsb-0002Xy-81 for qemu-devel@nongnu.org; Sat, 21 Jun 2014 08:58:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WyKsU-0007Wk-7a for qemu-devel@nongnu.org; Sat, 21 Jun 2014 08:58:49 -0400 Received: from mail-wg0-x22e.google.com ([2a00:1450:400c:c00::22e]:45086) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WyKsT-0007WD-U0 for qemu-devel@nongnu.org; Sat, 21 Jun 2014 08:58:42 -0400 Received: by mail-wg0-f46.google.com with SMTP id y10so4799744wgg.29 for ; Sat, 21 Jun 2014 05:58:41 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Sat, 21 Jun 2014 14:58:17 +0200 Message-Id: <1403355502-12288-7-git-send-email-pbonzini@redhat.com> In-Reply-To: <1403355502-12288-1-git-send-email-pbonzini@redhat.com> References: <1403355502-12288-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH v3 06/11] target-arm: implement SCTLR.EE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Set CPSR.E to SCTLR.EE on exception, and use SCTLR.EE also to determine endianness for loads during TLB misses. Signed-off-by: Paolo Bonzini --- target-arm/helper.c | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6e4fc55..2e3816d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3213,6 +3213,30 @@ void switch_mode(CPUARMState *env, int mode) env->spsr = env->banked_spsr[i]; } +static uint32_t ldl_ptw_phys(CPUState *cs, target_ulong physaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + if (unlikely(env->cp15.c1_sys & SCTLR_EE)) { + return ldl_be_phys(cs->as, physaddr); + } else { + return ldl_le_phys(cs->as, physaddr); + } +} + +static uint64_t ldq_ptw_phys(CPUState *cs, target_ulong physaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + if (unlikely(env->cp15.c1_sys & SCTLR_EE)) { + return ldq_be_phys(cs->as, physaddr); + } else { + return ldq_le_phys(cs->as, physaddr); + } +} + static void v7m_push(CPUARMState *env, uint32_t val) { CPUState *cs = CPU(arm_env_get_cpu(env)); @@ -3483,7 +3507,9 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Clear IT bits. */ env->condexec_bits = 0; /* Switch to the new mode, and to the correct instruction set. */ - env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; + env->uncached_cpsr = (env->uncached_cpsr & ~(CPSR_M | CPSR_E)) + | new_mode + | (env->cp15.c1_sys & SCTLR_EE ? CPSR_E : 0); env->daif |= mask; /* this is a lie, as the was no c1_sys on V4T/V5, but who cares * and we should just guard the thumb mode on V4 */ @@ -3592,7 +3618,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, code = 5; goto do_fault; } - desc = ldl_phys(cs->as, table); + desc = ldl_ptw_phys(cs, table); type = (desc & 3); domain = (desc >> 5) & 0x0f; domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; @@ -3623,7 +3649,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, /* Fine pagetable. */ table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc = ldl_phys(cs->as, table); + desc = ldl_ptw_phys(cs, table); switch (desc & 3) { case 0: /* Page translation fault. */ code = 7; @@ -3694,7 +3720,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, code = 5; goto do_fault; } - desc = ldl_phys(cs->as, table); + desc = ldl_ptw_phys(cs, table); type = (desc & 3); if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { /* Section translation fault, or attempt to use the encoding @@ -3736,7 +3762,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, } /* Lookup l2 entry. */ table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc = ldl_phys(cs->as, table); + desc = ldl_ptw_phys(cs, table); ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); switch (desc & 3) { case 0: /* Page translation fault. */ @@ -3930,7 +3956,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, descaddr |= (address >> (granule_sz * (4 - level))) & descmask; descaddr &= ~7ULL; - descriptor = ldq_phys(cs->as, descaddr); + descriptor = ldq_ptw_phys(cs, descaddr); if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { /* Invalid, or the Reserved level 3 encoding */ -- 1.9.3