[PATCH v02 3/7] arm: omap: introduce iommu translation for GPU remoteproc

[Andrii Tseglytskyi <andrii.tseglytskyi@globallogic.com>]

The following patch introduced platform specific MMU data
definitions and pagetable translation function for OMAP5 GPU
remoteproc. Typically GPU MMU performs uses two level address
translation, so algorithm is quite straightforward here -
pagetables are enumerated and all pfns are updated with
corresponding mfns.

Current patch adds functionality, needed for proper handling of
GPU MMU, which is very similar to existing IPU/DSP MMUs.

Change-Id: I129da9485c61cc94801c6b243498e31db33f5d30
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@globallogic.com>
---
 xen/arch/arm/platforms/omap_iommu.c |   86 +++++++++++++++++++++++++++++++++++
 xen/arch/arm/remoteproc_iommu.c     |    1 +
 xen/include/xen/remoteproc_iommu.h  |    1 +
 3 files changed, 88 insertions(+)

diff --git a/xen/arch/arm/platforms/omap_iommu.c b/xen/arch/arm/platforms/omap_iommu.c
index e0c4633..bbaa7bc 100644
--- a/xen/arch/arm/platforms/omap_iommu.c
+++ b/xen/arch/arm/platforms/omap_iommu.c
@@ -32,12 +32,23 @@
 /* register where address of pagetable is stored */
 #define MMU_IPU_TTB_OFFSET          0x4c
 
+#define MMU_SGX_TTB_OFFSET_00		0xc84
+#define MMU_SGX_TTB_OFFSET_01		0xc38
+#define MMU_SGX_TTB_OFFSET_02		0xc3c
+#define MMU_SGX_TTB_OFFSET_03		0xc40
+#define MMU_SGX_TTB_OFFSET_04		0xc44
+#define MMU_SGX_TTB_OFFSET_05		0xc48
+#define MMU_SGX_TTB_OFFSET_06		0xc4c
+#define MMU_SGX_TTB_OFFSET_07		0xc50
+
 /* 1st level translation */
 #define MMU_OMAP_PGD_SHIFT          20
 #define MMU_OMAP_SUPER_SHIFT        24	/* "supersection" - 16 Mb */
 #define MMU_OMAP_SECTION_SHIFT      20	/* "section"  - 1 Mb */
 #define MMU_OMAP_SECOND_LEVEL_SHIFT 10
 
+#define MMU_SGX_PGD_SHIFT			22	/* SGX section */
+
 /* 2nd level translation */
 #define MMU_OMAP_PTE_SMALL_SHIFT    12	/* "small page" - 4Kb */
 #define MMU_OMAP_PTE_LARGE_SHIFT    16	/* "large page" - 64 Kb */
@@ -57,13 +68,26 @@
 #define PTE_LARGE       (1 << 0)
 
 #define	OMAP_IPU_MMU_MEM_BASE   0x55082000
+#define	OMAP_SGX_MMU_MEM_BASE	0x56000000
 
 static u32 mmu_ipu_translate_pagetable(struct mmu_info *mmu, struct mmu_pagetable *pgt);
+static u32 mmu_sgx_translate_pagetable(struct mmu_info *mmu, struct mmu_pagetable *pgt);
 
 static u32 ipu_trap_offsets[] = {
     MMU_IPU_TTB_OFFSET,
 };
 
+static u32 sgx_trap_offsets[] = {
+    MMU_SGX_TTB_OFFSET_00,
+    MMU_SGX_TTB_OFFSET_01,
+    MMU_SGX_TTB_OFFSET_02,
+    MMU_SGX_TTB_OFFSET_03,
+    MMU_SGX_TTB_OFFSET_04,
+    MMU_SGX_TTB_OFFSET_05,
+    MMU_SGX_TTB_OFFSET_06,
+    MMU_SGX_TTB_OFFSET_07,
+};
+
 static const struct pagetable_data pagetable_ipu_data = {
     .pgd_shift          = MMU_OMAP_PGD_SHIFT,
     .super_shift        = MMU_OMAP_SUPER_SHIFT,
@@ -82,6 +106,23 @@ struct mmu_info omap_ipu_mmu = {
     .translate_pfunc	= mmu_ipu_translate_pagetable,
 };
 
+static const struct pagetable_data pagetable_sgx_data = {
+    .pgd_shift      = MMU_SGX_PGD_SHIFT,
+    .super_shift    = MMU_SGX_PGD_SHIFT,
+    .section_shift  = MMU_SGX_PGD_SHIFT,
+    .pte_shift      = MMU_OMAP_PTE_SMALL_SHIFT,	/* the same as IPU */
+};
+
+struct mmu_info omap_sgx_mmu = {
+    .name           = "SGX_L2_MMU",
+    .pg_data        = &pagetable_sgx_data,
+    .trap_offsets   = sgx_trap_offsets,
+    .mem_start      = OMAP_SGX_MMU_MEM_BASE,
+    .mem_size       = 0x1000,
+    .num_traps      = ARRAY_SIZE(sgx_trap_offsets),
+    .translate_pfunc    = mmu_sgx_translate_pagetable,
+};
+
 static bool translate_supersections_to_pages = true;
 static bool translate_sections_to_pages = true;
 
@@ -237,6 +278,51 @@ static u32 mmu_ipu_translate_pagetable(struct mmu_info *mmu, struct mmu_pagetabl
     return __pa(hyp_pgt);
 }
 
+static u32 mmu_sgx_translate_pagetable(struct mmu_info *mmu, struct mmu_pagetable *pgt)
+{
+    u32 *kern_pgt, *hyp_pgt;
+    u32 i;
+
+    ASSERT(mmu);
+    ASSERT(pgt);
+
+    kern_pgt = pgt->kern_pagetable;
+    hyp_pgt = pgt->hyp_pagetable;
+    pgt->page_counter = 0;
+
+    /* 1-st level translation */
+    for ( i = 0; i < MMU_PTRS_PER_PGD(mmu); i++ )
+    {
+        paddr_t pd_maddr, pd_paddr, pd_flags;
+        u32 pgd, pd_mask = MMU_SECTION_MASK(mmu->pg_data->pte_shift);
+
+        pgd = kern_pgt[i];
+        if ( !pgd )
+        {
+            /* handle the case when second level translation table
+             * was removed from kernel */
+            if ( unlikely(hyp_pgt[i]) )
+            {
+                xfree(__va(hyp_pgt[i] & pd_mask));
+                hyp_pgt[i] = 0;
+            }
+            continue;
+        }
+
+        pd_paddr = pgd & pd_mask;
+        pd_flags = pgd & ~pd_mask;
+        pd_maddr = p2m_lookup(current->domain, pd_paddr, NULL);
+        ASSERT(pd_maddr != INVALID_PADDR);
+
+        /* 2-nd level translation */
+        hyp_pgt[i] = mmu_translate_second_level(mmu, pgt, pd_maddr, hyp_pgt[i]);
+        hyp_pgt[i] |= pd_flags;
+    }
+
+    clean_and_invalidate_xen_dcache_va_range(hyp_pgt, MMU_PGD_TABLE_SIZE(mmu));
+    return __pa(hyp_pgt);
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/xen/arch/arm/remoteproc_iommu.c b/xen/arch/arm/remoteproc_iommu.c
index 8291f3f..3b3da3b 100644
--- a/xen/arch/arm/remoteproc_iommu.c
+++ b/xen/arch/arm/remoteproc_iommu.c
@@ -34,6 +34,7 @@
 
 static struct mmu_info *mmu_list[] = {
     &omap_ipu_mmu,
+    &omap_sgx_mmu,
 };
 
 #define mmu_for_each(pfunc, data)                       \
diff --git a/xen/include/xen/remoteproc_iommu.h b/xen/include/xen/remoteproc_iommu.h
index ff1c439..d69c85e 100644
--- a/xen/include/xen/remoteproc_iommu.h
+++ b/xen/include/xen/remoteproc_iommu.h
@@ -77,5 +77,6 @@ u32 mmu_translate_second_level(struct mmu_info *mmu, struct mmu_pagetable *pgt,
                                u32 maddr, u32 hyp_addr);
 
 extern struct mmu_info omap_ipu_mmu;
+extern struct mmu_info omap_sgx_mmu;
 
 #endif /* _REMOTEPROC_IOMMU_H_ */
-- 
1.7.9.5