From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47611) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X0Uhk-0003LG-4R for qemu-devel@nongnu.org; Fri, 27 Jun 2014 07:52:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X0Uhe-00083a-2K for qemu-devel@nongnu.org; Fri, 27 Jun 2014 07:52:32 -0400 From: Alexander Graf Date: Fri, 27 Jun 2014 13:51:53 +0200 Message-Id: <1403869944-31927-2-git-send-email-agraf@suse.de> In-Reply-To: <1403869944-31927-1-git-send-email-agraf@suse.de> References: <1403869944-31927-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 01/32] linux-user: Correct AUXV Cache Line Sizes for PowerPC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Tom Musta From: Tom Musta Set the AT_ICACHEBSIZE and AT_DCACHEBSIZE entries of the AUXV to match the CPU model's cache line sizes. This fixes memory clobbering problems on more recent Book 3s implementations; memset(p, 0, N) will use the dcbz instruction when N is sufficiently large and many of the newer server CPUs have cache lines sizes of 128 bytes. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- linux-user/elfload.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1248eda..64d23fa 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -774,8 +774,9 @@ static uint32_t get_elf_hwcap(void) #define DLINFO_ARCH_ITEMS 5 #define ARCH_DLINFO \ do { \ - NEW_AUX_ENT(AT_DCACHEBSIZE, 0x20); \ - NEW_AUX_ENT(AT_ICACHEBSIZE, 0x20); \ + PowerPCCPU *cpu = POWERPC_CPU(thread_cpu); \ + NEW_AUX_ENT(AT_DCACHEBSIZE, cpu->env.dcache_line_size); \ + NEW_AUX_ENT(AT_ICACHEBSIZE, cpu->env.icache_line_size); \ NEW_AUX_ENT(AT_UCACHEBSIZE, 0); \ /* \ * Now handle glibc compatibility. \ -- 1.8.1.4