From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1IRg-0008Cq-NB for qemu-devel@nongnu.org; Sun, 29 Jun 2014 12:59:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1IRb-0003Ps-T4 for qemu-devel@nongnu.org; Sun, 29 Jun 2014 12:59:16 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49399) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1IRb-0003Pl-KK for qemu-devel@nongnu.org; Sun, 29 Jun 2014 12:59:11 -0400 Date: Sun, 29 Jun 2014 19:59:32 +0300 From: "Michael S. Tsirkin" Message-ID: <1404060115-27410-26-git-send-email-mst@redhat.com> References: <1404060115-27410-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1404060115-27410-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL 25/37] cpu: introduce CPUClass::virtio_is_big_endian() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?us-ascii?B?PT9VVEYtOD9xP0FuZHJlYXM9MjBGPUMzPUE0cmJlcj89?= , Anthony Liguori , Greg Kurz From: Greg Kurz If we want to support targets that can change endianness (modern PPC and ARM for the moment), we need to add a per-CPU class method to be called from the virtio code. The virtio_ prefix in the name is a hint for people to avoid misusage (aka. anywhere but from the virtio code). The default behaviour is to return the compile-time default target endianness. Suggested-by: Peter Maydell Signed-off-by: Greg Kurz Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/qom/cpu.h | 1 + qom/cpu.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4b352a2..1aafbf5 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -116,6 +116,7 @@ typedef struct CPUClass { CPUUnassignedAccess do_unassigned_access; void (*do_unaligned_access)(CPUState *cpu, vaddr addr, int is_write, int is_user, uintptr_t retaddr); + bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, diff --git a/qom/cpu.c b/qom/cpu.c index fada2d4..b32dd0a 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -196,6 +196,11 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg) return 0; } +bool target_words_bigendian(void); +static bool cpu_common_virtio_is_big_endian(CPUState *cpu) +{ + return target_words_bigendian(); +} void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags) @@ -334,6 +339,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->write_elf64_note = cpu_common_write_elf64_note; k->gdb_read_register = cpu_common_gdb_read_register; k->gdb_write_register = cpu_common_gdb_write_register; + k->virtio_is_big_endian = cpu_common_virtio_is_big_endian; dc->realize = cpu_common_realizefn; /* * Reason: CPUs still need special care by board code: wiring up -- MST