From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4CR8-0004R8-LJ for qemu-devel@nongnu.org; Mon, 07 Jul 2014 13:10:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X4CR1-0005Vd-5m for qemu-devel@nongnu.org; Mon, 07 Jul 2014 13:10:42 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:10583) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4CR0-0005V4-Kd for qemu-devel@nongnu.org; Mon, 07 Jul 2014 13:10:34 -0400 From: Bastian Koppelmann Date: Mon, 7 Jul 2014 19:13:27 +0100 Message-Id: <1404756822-3253-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Hi, my aim is to add Infineon's TriCore architecture to QEMU. This series of patches adds the target stubs, a basic testboard and a softmmu for system mode emulation. Furthermore it adds all the 16 bit long instructions of the architecture grouped by opcode format. After this series of patches. Another one will follow, which adds a lot of the 32 bit long instructions. Peter Maydall: Sorry if i spammed you with mails. The --cc option of git confused me a little bit, which resulted in a SMTP 550 error. All the best Bastian Bastian Koppelmann (15): target-tricore: Add target stubs and qom-cpu target-tricore: Add board for systemmode target-tricore: Add softmmu support target-tricore: Add initialization for translation target-tricore: Add masks and opcodes for decoding target-tricore: Add instructions of SRC opcode format target-tricore: Add instructions of SRR opcode format target-tricore: Add instructions of SSR opcode format target-tricore: Add instructions of SRRS and SLRO opcode format. target-tricore: Add instructions of SB opcode format target-tricore: Add instructions of SBC and SBRN opcode format target-tricore: Add instructions of SBR opcode format target-tricore: Add instructions of SC opcode format target-tricore: Add instructions of SLR, SSRO and SRO opcode format target-tricore: Add instructions of SR opcode format arch_init.c | 2 + configure | 13 + cpu-exec.c | 11 +- cpus.c | 6 + default-configs/tricore-softmmu.mak | 3 + hw/tricore/Makefile.objs | 1 + hw/tricore/tricore_testboard.c | 130 ++++ include/elf.h | 2 + include/hw/tricore/tricore.h | 54 ++ include/sysemu/arch_init.h | 1 + target-tricore/Makefile.objs | 2 + target-tricore/cpu-qom.h | 71 ++ target-tricore/cpu.c | 121 +++ target-tricore/cpu.h | 380 ++++++++++ target-tricore/helper.c | 88 +++ target-tricore/helper.h | 25 + target-tricore/machine.c | 21 + target-tricore/op_helper.c | 384 ++++++++++ target-tricore/translate.c | 1198 +++++++++++++++++++++++++++++ target-tricore/translate_init.c | 51 ++ target-tricore/tricore-defs.h | 28 + target-tricore/tricore-opcodes.h | 1405 +++++++++++++++++++++++++++++++++++ user-exec.c | 17 + 23 files changed, 4013 insertions(+), 1 deletion(-) create mode 100644 default-configs/tricore-softmmu.mak create mode 100644 hw/tricore/Makefile.objs create mode 100644 hw/tricore/tricore_testboard.c create mode 100644 include/hw/tricore/tricore.h create mode 100644 target-tricore/Makefile.objs create mode 100644 target-tricore/cpu-qom.h create mode 100644 target-tricore/cpu.c create mode 100644 target-tricore/cpu.h create mode 100644 target-tricore/helper.c create mode 100644 target-tricore/helper.h create mode 100644 target-tricore/machine.c create mode 100644 target-tricore/op_helper.c create mode 100644 target-tricore/translate.c create mode 100644 target-tricore/translate_init.c create mode 100644 target-tricore/tricore-defs.h create mode 100644 target-tricore/tricore-opcodes.h -- 2.0.1