From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4CRC-0004Rn-Jx for qemu-devel@nongnu.org; Mon, 07 Jul 2014 13:10:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X4CR6-0005Za-I7 for qemu-devel@nongnu.org; Mon, 07 Jul 2014 13:10:46 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:10632) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4CR6-0005Z0-8q for qemu-devel@nongnu.org; Mon, 07 Jul 2014 13:10:40 -0400 From: Bastian Koppelmann Date: Mon, 7 Jul 2014 19:13:41 +0100 Message-Id: <1404756822-3253-15-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1404756822-3253-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1404756822-3253-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH 14/15] target-tricore: Add instructions of SLR, SSRO and SRO opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Add instructions of SLR, SSRO and SRO opcode format. Signed-off-by: Bastian Koppelmann --- target-tricore/translate.c | 149 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index e98af65..628bd8b 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -783,6 +783,155 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx) const16 = MASK_OP_SC_CONST8(ctx->opcode); tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); break; +/* SLR-format */ + case OPC1_16_SLR_LD_A: + r1 = MASK_OP_SLR_D(ctx->opcode); + r2 = MASK_OP_SLR_S2(ctx->opcode); + tcg_gen_qemu_ld32s(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx); + break; + case OPC1_16_SLR_LD_A_POSTINC: + r1 = MASK_OP_SLR_D(ctx->opcode); + r2 = MASK_OP_SLR_S2(ctx->opcode); + tcg_gen_qemu_ld32s(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); + break; + case OPC1_16_SLR_LD_BU: + r1 = MASK_OP_SLR_D(ctx->opcode); + r2 = MASK_OP_SLR_S2(ctx->opcode); + tcg_gen_qemu_ld8u(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx); + break; + case OPC1_16_SLR_LD_BU_POSTINC: + r1 = MASK_OP_SLR_D(ctx->opcode); + r2 = MASK_OP_SLR_S2(ctx->opcode); + tcg_gen_qemu_ld8u(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); + break; + case OPC1_16_SLR_LD_H: + r1 = MASK_OP_SLR_D(ctx->opcode); + r2 = MASK_OP_SLR_S2(ctx->opcode); + tcg_gen_qemu_ld16s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx); + break; + case OPC1_16_SLR_LD_H_POSTINC: + r1 = MASK_OP_SLR_D(ctx->opcode); + r2 = MASK_OP_SLR_S2(ctx->opcode); + tcg_gen_qemu_ld16s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); + break; + case OPC1_16_SLR_LD_W: + r1 = MASK_OP_SLR_D(ctx->opcode); + r2 = MASK_OP_SLR_S2(ctx->opcode); + tcg_gen_qemu_ld32s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx); + break; + case OPC1_16_SLR_LD_W_POSTINC: + r1 = MASK_OP_SLR_D(ctx->opcode); + r2 = MASK_OP_SLR_S2(ctx->opcode); + tcg_gen_qemu_ld32s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); + break; +/* SRO-format */ + case OPC1_16_SRO_LD_A: + address = MASK_OP_SRO_OFF4(ctx->opcode); + r2 = MASK_OP_SRO_S2(ctx->opcode); + gen_indirect_ld32s(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4); + break; + case OPC1_16_SRO_LD_BU: + r1 = MASK_OP_SRO_S2(ctx->opcode); + const16 = MASK_OP_SRO_OFF4(ctx->opcode); + gen_indirect_ld8u(ctx, cpu_gpr_d[15], cpu_gpr_a[r1], const16); + break; + case OPC1_16_SRO_LD_H: + r1 = MASK_OP_SRO_S2(ctx->opcode); + const16 = MASK_OP_SRO_OFF4(ctx->opcode); + gen_indirect_ld16s(ctx, cpu_gpr_d[15], cpu_gpr_a[r1], const16); + break; + case OPC1_16_SRO_LD_W: + address = MASK_OP_SRO_OFF4(ctx->opcode); + r2 = MASK_OP_SRO_S2(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address * 4); + tcg_gen_qemu_ld32u(cpu_gpr_d[15], temp, ctx->mem_idx); + tcg_temp_free(temp); + break; + case OPC1_16_SRO_ST_A: + const16 = MASK_OP_SRO_OFF4(ctx->opcode); + r1 = MASK_OP_SRO_S2(ctx->opcode); + gen_indirect_st32(ctx, cpu_gpr_a[15], cpu_gpr_a[r1], const16 * 4); + break; + case OPC1_16_SRO_ST_B: + r1 = MASK_OP_SRO_S2(ctx->opcode); + const16 = MASK_OP_SRO_OFF4(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0xff); + gen_indirect_st8(ctx, temp, cpu_gpr_a[r1], const16); + tcg_temp_free(temp); + break; + case OPC1_16_SRO_ST_H: + r1 = MASK_OP_SRO_S2(ctx->opcode); + const16 = MASK_OP_SRO_OFF4(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0xffff); + gen_indirect_st16(ctx, temp, cpu_gpr_a[r1], const16 * 2); + tcg_temp_free(temp); + break; + case OPC1_16_SRO_ST_W: + r1 = MASK_OP_SRO_S2(ctx->opcode); + const16 = MASK_OP_SRO_OFF4(ctx->opcode); + gen_indirect_st32(ctx, cpu_gpr_d[15], cpu_gpr_a[r1], const16 * 4); + break; +/* SSRO-format */ + case OPC1_16_SSRO_ST_A: + r1 = MASK_OP_SSRO_S1(ctx->opcode); + const16 = MASK_OP_SSRO_OFF4(ctx->opcode); + gen_indirect_st32(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4); + break; + case OPC1_16_SSRO_ST_B: + r1 = MASK_OP_SSRO_S1(ctx->opcode); + const16 = MASK_OP_SSRO_OFF4(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff); + gen_indirect_st8(ctx, temp, cpu_gpr_a[15], const16); + tcg_temp_free(temp); + break; + case OPC1_16_SSRO_ST_H: + r1 = MASK_OP_SSRO_S1(ctx->opcode); + const16 = MASK_OP_SSRO_OFF4(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff); + gen_indirect_st16(ctx, temp, cpu_gpr_a[15], const16 * 2); + tcg_temp_free(temp); + break; + case OPC1_16_SSRO_ST_W: + r1 = MASK_OP_SSRO_S1(ctx->opcode); + const16 = MASK_OP_SSRO_OFF4(ctx->opcode); + gen_indirect_st32(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4); + break; +/* SSRO-format */ + case OPC1_16_SSRO_ST_A: + r1 = MASK_OP_SSRO_S1(ctx->opcode); + const16 = MASK_OP_SSRO_OFF4(ctx->opcode); + gen_indirect_st32(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4); + break; + case OPC1_16_SSRO_ST_B: + r1 = MASK_OP_SSRO_S1(ctx->opcode); + const16 = MASK_OP_SSRO_OFF4(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff); + gen_indirect_st8(ctx, temp, cpu_gpr_a[15], const16); + tcg_temp_free(temp); + break; + case OPC1_16_SSRO_ST_H: + r1 = MASK_OP_SSRO_S1(ctx->opcode); + const16 = MASK_OP_SSRO_OFF4(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff); + gen_indirect_st16(ctx, temp, cpu_gpr_a[15], const16 * 2); + tcg_temp_free(temp); + break; + case OPC1_16_SSRO_ST_W: + r1 = MASK_OP_SSRO_S1(ctx->opcode); + const16 = MASK_OP_SSRO_OFF4(ctx->opcode); + gen_indirect_st32(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4); + break; } } -- 2.0.1