* [PATCH v7 0/4] ARM: Exynos: PMU cleanup and refactoring for using DT
@ 2014-07-09 4:00 ` Pankaj Dubey
0 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: kgene.kim, linux, t.figa, vikas.sajjan, joshi, naushad,
thomas.ab, chow.kim, Pankaj Dubey
This patch series, modifies Exynos Power Management Unit (PMU) related code
for converting it into a platform_driver. This is also preparation for moving
PMU related code out of machine folder into a either "drivers/mfd", or
"drivers/power" or some other suitable place so that ARM64 based SoC can
utilize common piece of code.
These patches are created on top of Kukjin Kim's for-next.
I have tested this patches on Exynos5250 Snow board for system boot and S2R.
This patch series depends on following two patch series:
[1]: mfd: syscon: Decouple syscon interface from syscon devices.
https://lkml.org/lkml/2014/6/24/188
[2]: Cleanup patches for mach-exynos.
http://www.spinics.net/lists/arm-kernel/msg341474.html
Patch v6 and discussion can be found here:
https://lkml.org/lkml/2014/7/7/22
Change since v6:
- Removed NULL check for pmu_data in pmu.c.
- Moved pmu_raw_readl and pmu_raw_writel inline helper function
into common.h.
Change Since v5:
- Squashed patch "Move "mach/map.h" inclusion from regs-pmu.h to platsmp.c"
into patch "Refactored code for using PMU address via DT".
- Addressed review comments from Tomasz Figa.
- Using init_irq machine function to initialize PMU mapping instead
of init_time.
- Rebased on latest Kukjin Kim's for-next branch.
Changes Since v4:
- Splitted patch series in two parts. Part 1 has code cleanup under mach-exynos
and posted as separate patch [2]. Current patchset is part 2 which modified
exynos pmu implementation for making it platform driver.
- Removed dependency over early_syscon API.
- Removed usage of regmap read/write APIs.
- Modified probe function to register exynos pmu as syscon provider using
Tomasz Figa's syscon patch [1].
- Address various other review comments from Tomasz Figa.
- Removed signed-off-by of Young-Gun Jang <yg1004.jang@samsung.com>,
as this id is no more valid. Taking ownership of all his patches.
Changes Since v3:
- Optimized exynos_pmu_probe function by removing exynos_pmu_data_init
as suggested by Vikas Sajjan.
- Modified syscon_early_regmap_lookup_by_phandle and
syscon_regmap_lookup_by_phandle function call to pass property as NULL.
Changes Since v2:
- Rebased on top of Daniel Lezcano's Exynos cpuidle refactor patches.
- Removed early mapping of PMU base address from exynos.c and removed
"get_exynos_pmuaddr" function. Instead of this added code in platsmp.c
to get PMU base address using of_iomap as suggested by Tomasz Figa.
- Converted PMU implementation into platform_driver by using static
platform_device method.
Changes Since v1:
- Rebased on latest for-next of Kukjin Kim's tree.
- Updated patch: Add support for mapping PMU base address via DT
- Removed __initdata from declaration of "exynos_pmu_base", as it caused
kernel crash as pointed out by Vikas Sajjan.
- Added support for Syscon initialization and getting PMU regmap handle
as suggested by Sylwester. Since current implementation of early
intialization [1] has limitation that "early_syscon_init" requires
DT to be unflattened and system should be able to allocate memory,
we can't use regmap handles for platsmp.c file as "smp_secondary_init"
will be called before DT unflattening. So I have kept both method for
accessing PMU base address. platsmp.c will use ioremmaped address where
as rest other files can use regmap handle.
- Updated patch: Refactored code for PMU register mapping via DT
- Modified to use regmap_read/write when using regmap handle.
- Added patch: Add device tree based initialization support for PMU.
- Convert existing PMU implementation to be a device tree based
before moving it to "drivers/mfd" folder. As suggested by Bartlomiej.
- Dropped making a platform_driver for PMU, as currently PMU binding
has two compatibility strings as "samsung, exynosxxx-pmu", "syscon",
once we enable MFD_SYSCON config option, current "syscon" driver probe
gets called and PMU probe never gets called. So modified PMU
initialization code to scan DT and match against supported compatiblity
string in driver code, and once we get matching node use that for
accessing PMU regmap handle using "syscon_early_regmap_lookup_by_phandle".
If there is any better solution please suggest.
Pankaj Dubey (4):
ARM: EXYNOS: Add support for mapping PMU base address via DT
ARM: EXYNOS: Refactored code for using PMU address via DT
ARM: EXYNOS: Add platform driver support for Exynos PMU
ARM: EXYNOS: Move PMU specific definitions from common.h
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/common.h | 28 +-
arch/arm/mach-exynos/exynos-pmu.h | 24 ++
arch/arm/mach-exynos/exynos.c | 49 ++-
arch/arm/mach-exynos/include/mach/map.h | 3 -
arch/arm/mach-exynos/mcpm-exynos.c | 8 +-
arch/arm/mach-exynos/platsmp.c | 4 +-
arch/arm/mach-exynos/pm.c | 77 ++--
arch/arm/mach-exynos/pmu.c | 225 ++++++++---
arch/arm/mach-exynos/regs-pmu.h | 522 +++++++++++++-------------
arch/arm/plat-samsung/include/plat/map-s5p.h | 1 -
11 files changed, 555 insertions(+), 387 deletions(-)
create mode 100644 arch/arm/mach-exynos/exynos-pmu.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 0/4] ARM: Exynos: PMU cleanup and refactoring for using DT
@ 2014-07-09 4:00 ` Pankaj Dubey
0 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel
This patch series, modifies Exynos Power Management Unit (PMU) related code
for converting it into a platform_driver. This is also preparation for moving
PMU related code out of machine folder into a either "drivers/mfd", or
"drivers/power" or some other suitable place so that ARM64 based SoC can
utilize common piece of code.
These patches are created on top of Kukjin Kim's for-next.
I have tested this patches on Exynos5250 Snow board for system boot and S2R.
This patch series depends on following two patch series:
[1]: mfd: syscon: Decouple syscon interface from syscon devices.
https://lkml.org/lkml/2014/6/24/188
[2]: Cleanup patches for mach-exynos.
http://www.spinics.net/lists/arm-kernel/msg341474.html
Patch v6 and discussion can be found here:
https://lkml.org/lkml/2014/7/7/22
Change since v6:
- Removed NULL check for pmu_data in pmu.c.
- Moved pmu_raw_readl and pmu_raw_writel inline helper function
into common.h.
Change Since v5:
- Squashed patch "Move "mach/map.h" inclusion from regs-pmu.h to platsmp.c"
into patch "Refactored code for using PMU address via DT".
- Addressed review comments from Tomasz Figa.
- Using init_irq machine function to initialize PMU mapping instead
of init_time.
- Rebased on latest Kukjin Kim's for-next branch.
Changes Since v4:
- Splitted patch series in two parts. Part 1 has code cleanup under mach-exynos
and posted as separate patch [2]. Current patchset is part 2 which modified
exynos pmu implementation for making it platform driver.
- Removed dependency over early_syscon API.
- Removed usage of regmap read/write APIs.
- Modified probe function to register exynos pmu as syscon provider using
Tomasz Figa's syscon patch [1].
- Address various other review comments from Tomasz Figa.
- Removed signed-off-by of Young-Gun Jang <yg1004.jang@samsung.com>,
as this id is no more valid. Taking ownership of all his patches.
Changes Since v3:
- Optimized exynos_pmu_probe function by removing exynos_pmu_data_init
as suggested by Vikas Sajjan.
- Modified syscon_early_regmap_lookup_by_phandle and
syscon_regmap_lookup_by_phandle function call to pass property as NULL.
Changes Since v2:
- Rebased on top of Daniel Lezcano's Exynos cpuidle refactor patches.
- Removed early mapping of PMU base address from exynos.c and removed
"get_exynos_pmuaddr" function. Instead of this added code in platsmp.c
to get PMU base address using of_iomap as suggested by Tomasz Figa.
- Converted PMU implementation into platform_driver by using static
platform_device method.
Changes Since v1:
- Rebased on latest for-next of Kukjin Kim's tree.
- Updated patch: Add support for mapping PMU base address via DT
- Removed __initdata from declaration of "exynos_pmu_base", as it caused
kernel crash as pointed out by Vikas Sajjan.
- Added support for Syscon initialization and getting PMU regmap handle
as suggested by Sylwester. Since current implementation of early
intialization [1] has limitation that "early_syscon_init" requires
DT to be unflattened and system should be able to allocate memory,
we can't use regmap handles for platsmp.c file as "smp_secondary_init"
will be called before DT unflattening. So I have kept both method for
accessing PMU base address. platsmp.c will use ioremmaped address where
as rest other files can use regmap handle.
- Updated patch: Refactored code for PMU register mapping via DT
- Modified to use regmap_read/write when using regmap handle.
- Added patch: Add device tree based initialization support for PMU.
- Convert existing PMU implementation to be a device tree based
before moving it to "drivers/mfd" folder. As suggested by Bartlomiej.
- Dropped making a platform_driver for PMU, as currently PMU binding
has two compatibility strings as "samsung, exynosxxx-pmu", "syscon",
once we enable MFD_SYSCON config option, current "syscon" driver probe
gets called and PMU probe never gets called. So modified PMU
initialization code to scan DT and match against supported compatiblity
string in driver code, and once we get matching node use that for
accessing PMU regmap handle using "syscon_early_regmap_lookup_by_phandle".
If there is any better solution please suggest.
Pankaj Dubey (4):
ARM: EXYNOS: Add support for mapping PMU base address via DT
ARM: EXYNOS: Refactored code for using PMU address via DT
ARM: EXYNOS: Add platform driver support for Exynos PMU
ARM: EXYNOS: Move PMU specific definitions from common.h
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/common.h | 28 +-
arch/arm/mach-exynos/exynos-pmu.h | 24 ++
arch/arm/mach-exynos/exynos.c | 49 ++-
arch/arm/mach-exynos/include/mach/map.h | 3 -
arch/arm/mach-exynos/mcpm-exynos.c | 8 +-
arch/arm/mach-exynos/platsmp.c | 4 +-
arch/arm/mach-exynos/pm.c | 77 ++--
arch/arm/mach-exynos/pmu.c | 225 ++++++++---
arch/arm/mach-exynos/regs-pmu.h | 522 +++++++++++++-------------
arch/arm/plat-samsung/include/plat/map-s5p.h | 1 -
11 files changed, 555 insertions(+), 387 deletions(-)
create mode 100644 arch/arm/mach-exynos/exynos-pmu.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 1/4] ARM: EXYNOS: Add support for mapping PMU base address via DT
2014-07-09 4:00 ` Pankaj Dubey
@ 2014-07-09 4:00 ` Pankaj Dubey
-1 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: kgene.kim, linux, t.figa, vikas.sajjan, joshi, naushad,
thomas.ab, chow.kim, Pankaj Dubey
Add support for mapping Samsung Power Management Unit (PMU)
base address from device tree.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/common.h | 1 +
arch/arm/mach-exynos/exynos.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 152b464..f8daa9c 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
extern void __iomem *sysram_ns_base_addr;
extern void __iomem *sysram_base_addr;
+extern void __iomem *pmu_base_addr;
void exynos_sysram_init(void);
void exynos_firmware_init(void);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 186f35d..173aac8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -19,6 +19,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
+#include <linux/irqchip.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
@@ -31,6 +32,8 @@
#include "regs-pmu.h"
#include "regs-sys.h"
+void __iomem *pmu_base_addr;
+
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
@@ -253,6 +256,39 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+static const struct of_device_id exynos_dt_pmu_match[] = {
+ { .compatible = "samsung,exynos3250-pmu" },
+ { .compatible = "samsung,exynos4210-pmu" },
+ { .compatible = "samsung,exynos4212-pmu" },
+ { .compatible = "samsung,exynos4412-pmu" },
+ { .compatible = "samsung,exynos5250-pmu" },
+ { .compatible = "samsung,exynos5420-pmu" },
+ { /*sentinel*/ },
+};
+
+static void exynos_map_pmu(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, exynos_dt_pmu_match);
+ if (np)
+ pmu_base_addr = of_iomap(np, 0);
+
+ if (!pmu_base_addr)
+ panic("failed to find exynos pmu register\n");
+}
+
+static void __init exynos_init_irq(void)
+{
+ irqchip_init();
+ /*
+ * Since platsmp.c needs pmu base address by the time
+ * DT is not unflatten so we can't use DT APIs before
+ * init_irq
+ */
+ exynos_map_pmu();
+}
+
static void __init exynos_dt_machine_init(void)
{
struct device_node *i2c_np;
@@ -336,6 +372,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
.smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_early = exynos_firmware_init,
+ .init_irq = exynos_init_irq,
.init_machine = exynos_dt_machine_init,
.init_late = exynos_init_late,
.dt_compat = exynos_dt_compat,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v7 1/4] ARM: EXYNOS: Add support for mapping PMU base address via DT
@ 2014-07-09 4:00 ` Pankaj Dubey
0 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel
Add support for mapping Samsung Power Management Unit (PMU)
base address from device tree.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/common.h | 1 +
arch/arm/mach-exynos/exynos.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 152b464..f8daa9c 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
extern void __iomem *sysram_ns_base_addr;
extern void __iomem *sysram_base_addr;
+extern void __iomem *pmu_base_addr;
void exynos_sysram_init(void);
void exynos_firmware_init(void);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 186f35d..173aac8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -19,6 +19,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
+#include <linux/irqchip.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
@@ -31,6 +32,8 @@
#include "regs-pmu.h"
#include "regs-sys.h"
+void __iomem *pmu_base_addr;
+
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
@@ -253,6 +256,39 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+static const struct of_device_id exynos_dt_pmu_match[] = {
+ { .compatible = "samsung,exynos3250-pmu" },
+ { .compatible = "samsung,exynos4210-pmu" },
+ { .compatible = "samsung,exynos4212-pmu" },
+ { .compatible = "samsung,exynos4412-pmu" },
+ { .compatible = "samsung,exynos5250-pmu" },
+ { .compatible = "samsung,exynos5420-pmu" },
+ { /*sentinel*/ },
+};
+
+static void exynos_map_pmu(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, exynos_dt_pmu_match);
+ if (np)
+ pmu_base_addr = of_iomap(np, 0);
+
+ if (!pmu_base_addr)
+ panic("failed to find exynos pmu register\n");
+}
+
+static void __init exynos_init_irq(void)
+{
+ irqchip_init();
+ /*
+ * Since platsmp.c needs pmu base address by the time
+ * DT is not unflatten so we can't use DT APIs before
+ * init_irq
+ */
+ exynos_map_pmu();
+}
+
static void __init exynos_dt_machine_init(void)
{
struct device_node *i2c_np;
@@ -336,6 +372,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
.smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_early = exynos_firmware_init,
+ .init_irq = exynos_init_irq,
.init_machine = exynos_dt_machine_init,
.init_late = exynos_init_late,
.dt_compat = exynos_dt_compat,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v7 2/4] ARM: EXYNOS: Refactored code for using PMU address via DT
2014-07-09 4:00 ` Pankaj Dubey
@ 2014-07-09 4:00 ` Pankaj Dubey
-1 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: kgene.kim, linux, t.figa, vikas.sajjan, joshi, naushad,
thomas.ab, chow.kim, Pankaj Dubey
Under "arm/mach-exynos" many files are using PMU register offsets.
Since we have added support for accessing PMU base address via DT,
now we can remove PMU mapping from exynosX_iodesc. Let's convert
all these access using iomapped address.
This will help us in removing static mapping of PMU base address
as well as help in reducing dependency over machine header files.
Thus helping for migration of PMU implementation from machine to
driver folder which can be reused for ARM64 bsed SoC.
Also as we have removed static mappings from "regs-pmu.h" it does
not need map.h anymore. But "platsmp.c" needed this and till now it
got included indirectly. So lets move header inclusion of
"mach/map.h" from "regs-pmu.h" to "platsmp.c".
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/common.h | 14 +-
arch/arm/mach-exynos/exynos.c | 12 +-
arch/arm/mach-exynos/include/mach/map.h | 3 -
arch/arm/mach-exynos/mcpm-exynos.c | 8 +-
arch/arm/mach-exynos/platsmp.c | 4 +-
arch/arm/mach-exynos/pm.c | 76 ++--
arch/arm/mach-exynos/pmu.c | 40 +-
arch/arm/mach-exynos/regs-pmu.h | 522 +++++++++++++-------------
arch/arm/plat-samsung/include/plat/map-s5p.h | 1 -
9 files changed, 339 insertions(+), 341 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f8daa9c..47b904b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -134,7 +134,7 @@ extern void exynos_cpu_die(unsigned int cpu);
/* PMU(Power Management Unit) support */
-#define PMU_TABLE_END NULL
+#define PMU_TABLE_END (-1U)
enum sys_powerdown {
SYS_AFTR,
@@ -144,7 +144,7 @@ enum sys_powerdown {
};
struct exynos_pmu_conf {
- void __iomem *reg;
+ unsigned int offset;
unsigned int val[NUM_SYS_POWERDOWN];
};
@@ -160,4 +160,14 @@ extern void exynos_enter_aftr(void);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
+static inline void pmu_raw_writel(u32 val, u32 offset)
+{
+ __raw_writel(val, pmu_base_addr + offset);
+}
+
+static inline u32 pmu_raw_readl(u32 offset)
+{
+ return __raw_readl(pmu_base_addr + offset);
+}
+
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 173aac8..d75d3e8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -61,11 +61,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = (unsigned long)S5P_VA_PMU,
- .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
- .length = SZ_64K,
- .type = MT_DEVICE,
- }, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
.length = SZ_4K,
@@ -139,11 +134,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
.length = 144 * SZ_1K,
.type = MT_DEVICE,
- }, {
- .virtual = (unsigned long)S5P_VA_PMU,
- .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
- .length = SZ_64K,
- .type = MT_DEVICE,
},
};
@@ -151,7 +141,7 @@ static void exynos_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
u32 val = 0x1;
- void __iomem *addr = EXYNOS_SWRESET;
+ void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
if (of_machine_is_compatible("samsung,exynos5440")) {
u32 status;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 963002f..f0b7e92 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -27,9 +27,6 @@
#define EXYNOS4_PA_SYSCON 0x10010000
#define EXYNOS5_PA_SYSCON 0x10050100
-#define EXYNOS4_PA_PMU 0x10020000
-#define EXYNOS5_PA_PMU 0x10040000
-
#define EXYNOS4_PA_CMU 0x10030000
#define EXYNOS5_PA_CMU 0x10010000
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 9315ba9..70e8ccd 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -55,7 +55,7 @@
"dsb\n\t" \
"ldmfd sp!, {fp, ip}" \
: \
- : "Ir" (S5P_INFORM0) \
+ : "Ir" (pmu_base_addr + S5P_INFORM0) \
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r9", "r10", "lr", "memory")
@@ -337,7 +337,7 @@ static int __init exynos_mcpm_init(void)
* To increase the stability of KFC reset we need to program
* the PMU SPARE3 register
*/
- __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
+ pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
exynos_mcpm_usage_count_init();
@@ -366,11 +366,11 @@ static int __init exynos_mcpm_init(void)
* turned on before the first man is powered up.
*/
for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
- value = __raw_readl(EXYNOS_COMMON_OPTION(i));
+ value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
EXYNOS5420_USE_L2_COMMON_UP_STATE;
- __raw_writel(value, EXYNOS_COMMON_OPTION(i));
+ pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
}
/*
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index cd25a9c..dab0784 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -26,6 +26,8 @@
#include <asm/smp_scu.h>
#include <asm/firmware.h>
+#include <mach/map.h>
+
#include "common.h"
#include "regs-pmu.h"
@@ -34,7 +36,7 @@ extern void exynos4_secondary_startup(void);
static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
- return S5P_INFORM5;
+ return pmu_base_addr + S5P_INFORM5;
return sysram_base_addr;
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index f127c0c..bcb96be 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -111,7 +111,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
*/
void exynos_cpu_power_down(int cpu)
{
- __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+ pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@@ -122,8 +122,8 @@ void exynos_cpu_power_down(int cpu)
*/
void exynos_cpu_power_up(int cpu)
{
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
- EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+ pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@@ -133,7 +133,7 @@ void exynos_cpu_power_up(int cpu)
*/
int exynos_cpu_power_state(int cpu)
{
- return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+ return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
S5P_CORE_LOCAL_PWR_EN);
}
@@ -143,7 +143,7 @@ int exynos_cpu_power_state(int cpu)
*/
void exynos_cluster_power_down(int cluster)
{
- __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
+ pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
}
/**
@@ -152,8 +152,8 @@ void exynos_cluster_power_down(int cluster)
*/
void exynos_cluster_power_up(int cluster)
{
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
- EXYNOS_COMMON_CONFIGURATION(cluster));
+ pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ EXYNOS_COMMON_CONFIGURATION(cluster));
}
/**
@@ -163,16 +163,20 @@ void exynos_cluster_power_up(int cluster)
*/
int exynos_cluster_power_state(int cluster)
{
- return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
+ return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
S5P_CORE_LOCAL_PWR_EN);
}
#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
- (sysram_base_addr + 0x24) : S5P_INFORM0))
+ pmu_base_addr + S5P_INFORM7 : \
+ (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+ (sysram_base_addr + 0x24) : \
+ pmu_base_addr + S5P_INFORM0))
#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
- (sysram_base_addr + 0x20) : S5P_INFORM1))
+ pmu_base_addr + S5P_INFORM6 : \
+ (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+ (sysram_base_addr + 0x20) : \
+ pmu_base_addr + S5P_INFORM1))
#define S5P_CHECK_AFTR 0xFCBA0D10
#define S5P_CHECK_SLEEP 0x00000BAD
@@ -180,7 +184,7 @@ int exynos_cluster_power_state(int cluster)
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos_set_wakeupmask(long mask)
{
- __raw_writel(mask, S5P_WAKEUP_MASK);
+ pmu_raw_writel(mask, S5P_WAKEUP_MASK);
}
static void exynos_cpu_set_boot_vector(long flags)
@@ -257,27 +261,27 @@ static void exynos_pm_prepare(void)
unsigned int tmp;
/* Set wake-up mask registers */
- __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
- __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+ pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+ pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
if (soc_is_exynos5250()) {
s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
- tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+ tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
- __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+ pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
/* Set value of power down register for sleep mode */
exynos_sys_powerdown_conf(SYS_SLEEP);
- __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
+ pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
- __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+ pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
static void exynos_pm_central_suspend(void)
@@ -285,9 +289,9 @@ static void exynos_pm_central_suspend(void)
unsigned long tmp;
/* Setting Central Sequence Register for power down mode */
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}
static int exynos_pm_suspend(void)
@@ -299,7 +303,7 @@ static int exynos_pm_suspend(void)
/* Setting SEQ_OPTION register */
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
- __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_save_register();
@@ -317,12 +321,12 @@ static int exynos_pm_central_resume(void)
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* clear the wakeup state register */
- __raw_writel(0x0, S5P_WAKEUP_STAT);
+ pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
return -1;
}
@@ -340,13 +344,13 @@ static void exynos_pm_resume(void)
/* For release retention */
- __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
if (soc_is_exynos5250())
s3c_pm_do_restore(exynos5_sys_save,
@@ -360,7 +364,7 @@ static void exynos_pm_resume(void)
early_wakeup:
/* Clear SLEEP mode set in INFORM1 */
- __raw_writel(0x0, S5P_INFORM1);
+ pmu_raw_writel(0x0, S5P_INFORM1);
return;
}
@@ -404,7 +408,7 @@ static int exynos_suspend_enter(suspend_state_t state)
s3c_pm_restore_uarts();
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
- __raw_readl(S5P_WAKEUP_STAT));
+ pmu_raw_readl(S5P_WAKEUP_STAT));
s3c_pm_check_restore();
@@ -475,9 +479,9 @@ void __init exynos_pm_init(void)
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
/* All wakeup disable */
- tmp = __raw_readl(S5P_WAKEUP_MASK);
+ tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
- __raw_writel(tmp, S5P_WAKEUP_MASK);
+ pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
register_syscore_ops(&exynos_pm_syscore_ops);
suspend_set_ops(&exynos_suspend_ops);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index dcfcb44..ff9d23f 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -18,7 +18,7 @@
static const struct exynos_pmu_conf *exynos_pmu_config;
static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
- /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+ /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@@ -212,7 +212,7 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
};
static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
- /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+ /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
@@ -315,7 +315,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
};
-static void __iomem * const exynos5_list_both_cnt_feed[] = {
+static unsigned int const exynos5_list_both_cnt_feed[] = {
EXYNOS5_ARM_CORE0_OPTION,
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_ARM_COMMON_OPTION,
@@ -329,7 +329,7 @@ static void __iomem * const exynos5_list_both_cnt_feed[] = {
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
};
-static void __iomem * const exynos5_list_diable_wfi_wfe[] = {
+static unsigned int const exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_FSYS_ARM_OPTION,
EXYNOS5_ISP_ARM_OPTION,
@@ -344,27 +344,27 @@ static void exynos5_init_pmu(void)
* Enable both SC_FEEDBACK and SC_COUNTER
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
- tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
+ tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
EXYNOS5_USE_SC_COUNTER);
- __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
+ pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
}
/*
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
*/
- tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
+ tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
- __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
+ pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
/*
* Disable WFI/WFE on XXX_OPTION
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
- tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
+ tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
EXYNOS5_OPTION_USE_STANDBYWFI);
- __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
+ pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
}
}
@@ -375,14 +375,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
if (soc_is_exynos5250())
exynos5_init_pmu();
- for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
- __raw_writel(exynos_pmu_config[i].val[mode],
- exynos_pmu_config[i].reg);
+ for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
+ pmu_raw_writel(exynos_pmu_config[i].val[mode],
+ exynos_pmu_config[i].offset);
if (soc_is_exynos4412()) {
- for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
- __raw_writel(exynos4412_pmu_config[i].val[mode],
- exynos4412_pmu_config[i].reg);
+ for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
+ pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
+ exynos4412_pmu_config[i].offset);
}
}
@@ -403,13 +403,13 @@ static int __init exynos_pmu_init(void)
* When SYS_WDTRESET is set, watchdog timer reset request
* is ignored by power management unit.
*/
- value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+ value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
value &= ~EXYNOS5_SYS_WDTRESET;
- __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+ pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
- value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+ value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
value &= ~EXYNOS5_SYS_WDTRESET;
- __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+ pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index e5e298c..96a1569 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -12,106 +12,102 @@
#ifndef __ASM_ARCH_REGS_PMU_H
#define __ASM_ARCH_REGS_PMU_H __FILE__
-#include <mach/map.h>
-
-#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
-
-#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
+#define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
-#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
+#define S5P_CENTRAL_SEQ_OPTION 0x0208
#define S5P_USE_STANDBY_WFI0 (1 << 16)
#define S5P_USE_STANDBY_WFE0 (1 << 24)
-#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
-#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
-
-#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
-#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
-#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
-
-#define S5P_INFORM0 S5P_PMUREG(0x0800)
-#define S5P_INFORM1 S5P_PMUREG(0x0804)
-#define S5P_INFORM5 S5P_PMUREG(0x0814)
-#define S5P_INFORM6 S5P_PMUREG(0x0818)
-#define S5P_INFORM7 S5P_PMUREG(0x081C)
-#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C)
-
-#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
-#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
-#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
-#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
-#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
-#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
-#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
-#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
-#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
-#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
-#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
-#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
-#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
-#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
-#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
-#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
-#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
-#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
-#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
-#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
-#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
-#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
-#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
-#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
-#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
-#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
-#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
-#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
-#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
-#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
-#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
-#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
-#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
-#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
-#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
-#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
-#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
-#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
-#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
-#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
-#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
-#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
-#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
-#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
-#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
-#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
-#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
-#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
-#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
-#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
-#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
-#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
-#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
-#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
-#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
-#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
-#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
-#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
-#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
-#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
-#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
-#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
-#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
-
-#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
+#define EXYNOS_SWRESET 0x0400
+#define EXYNOS5440_SWRESET 0x00C4
+
+#define S5P_WAKEUP_STAT 0x0600
+#define S5P_EINT_WAKEUP_MASK 0x0604
+#define S5P_WAKEUP_MASK 0x0608
+
+#define S5P_INFORM0 0x0800
+#define S5P_INFORM1 0x0804
+#define S5P_INFORM5 0x0814
+#define S5P_INFORM6 0x0818
+#define S5P_INFORM7 0x081C
+#define S5P_PMU_SPARE3 0x090C
+
+#define S5P_ARM_CORE0_LOWPWR 0x1000
+#define S5P_DIS_IRQ_CORE0 0x1004
+#define S5P_DIS_IRQ_CENTRAL0 0x1008
+#define S5P_ARM_CORE1_LOWPWR 0x1010
+#define S5P_DIS_IRQ_CORE1 0x1014
+#define S5P_DIS_IRQ_CENTRAL1 0x1018
+#define S5P_ARM_COMMON_LOWPWR 0x1080
+#define S5P_L2_0_LOWPWR 0x10C0
+#define S5P_L2_1_LOWPWR 0x10C4
+#define S5P_CMU_ACLKSTOP_LOWPWR 0x1100
+#define S5P_CMU_SCLKSTOP_LOWPWR 0x1104
+#define S5P_CMU_RESET_LOWPWR 0x110C
+#define S5P_APLL_SYSCLK_LOWPWR 0x1120
+#define S5P_MPLL_SYSCLK_LOWPWR 0x1124
+#define S5P_VPLL_SYSCLK_LOWPWR 0x1128
+#define S5P_EPLL_SYSCLK_LOWPWR 0x112C
+#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138
+#define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C
+#define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140
+#define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144
+#define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148
+#define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C
+#define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150
+#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158
+#define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C
+#define S5P_CMU_RESET_CAM_LOWPWR 0x1160
+#define S5P_CMU_RESET_TV_LOWPWR 0x1164
+#define S5P_CMU_RESET_MFC_LOWPWR 0x1168
+#define S5P_CMU_RESET_G3D_LOWPWR 0x116C
+#define S5P_CMU_RESET_LCD0_LOWPWR 0x1170
+#define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178
+#define S5P_CMU_RESET_GPS_LOWPWR 0x117C
+#define S5P_TOP_BUS_LOWPWR 0x1180
+#define S5P_TOP_RETENTION_LOWPWR 0x1184
+#define S5P_TOP_PWR_LOWPWR 0x1188
+#define S5P_LOGIC_RESET_LOWPWR 0x11A0
+#define S5P_ONENAND_MEM_LOWPWR 0x11C0
+#define S5P_G2D_ACP_MEM_LOWPWR 0x11C8
+#define S5P_USBOTG_MEM_LOWPWR 0x11CC
+#define S5P_HSMMC_MEM_LOWPWR 0x11D0
+#define S5P_CSSYS_MEM_LOWPWR 0x11D4
+#define S5P_SECSS_MEM_LOWPWR 0x11D8
+#define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200
+#define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204
+#define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220
+#define S5P_PAD_RETENTION_UART_LOWPWR 0x1224
+#define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228
+#define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C
+#define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230
+#define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234
+#define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240
+#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260
+#define S5P_XUSBXTI_LOWPWR 0x1280
+#define S5P_XXTI_LOWPWR 0x1284
+#define S5P_EXT_REGULATOR_LOWPWR 0x12C0
+#define S5P_GPIO_MODE_LOWPWR 0x1300
+#define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340
+#define S5P_CAM_LOWPWR 0x1380
+#define S5P_TV_LOWPWR 0x1384
+#define S5P_MFC_LOWPWR 0x1388
+#define S5P_G3D_LOWPWR 0x138C
+#define S5P_LCD0_LOWPWR 0x1390
+#define S5P_MAUDIO_LOWPWR 0x1398
+#define S5P_GPS_LOWPWR 0x139C
+#define S5P_GPS_ALIVE_LOWPWR 0x13A0
+
+#define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000
#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
(EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
#define EXYNOS_ARM_CORE_STATUS(_nr) \
(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
-#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500)
+#define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500
#define EXYNOS_COMMON_CONFIGURATION(_nr) \
(EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
#define EXYNOS_COMMON_STATUS(_nr) \
@@ -119,195 +115,195 @@
#define EXYNOS_COMMON_OPTION(_nr) \
(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
-#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
-#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
-#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
-#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
-#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
-#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
-#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
+#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
+#define S5P_PAD_RET_GPIO_OPTION 0x3108
+#define S5P_PAD_RET_UART_OPTION 0x3128
+#define S5P_PAD_RET_MMCA_OPTION 0x3148
+#define S5P_PAD_RET_MMCB_OPTION 0x3168
+#define S5P_PAD_RET_EBIA_OPTION 0x3188
+#define S5P_PAD_RET_EBIB_OPTION 0x31A8
#define S5P_CORE_LOCAL_PWR_EN 0x3
/* Only for EXYNOS4210 */
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
-#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
-#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
-#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
+#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
+#define S5P_MODIMIF_MEM_LOWPWR 0x11C4
+#define S5P_PCIE_MEM_LOWPWR 0x11E0
+#define S5P_SATA_MEM_LOWPWR 0x11E4
+#define S5P_LCD1_LOWPWR 0x1394
/* Only for EXYNOS4x12 */
-#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
-#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
-#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
-#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
-#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
-#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
-#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
-#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
-#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
-#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
-#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
-#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
-#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
-#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
-#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
-#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
-#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
-#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
-#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
-#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
-#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
-#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
-#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
-#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
-#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
-#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
-#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
-
-#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
-#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
-#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
-#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
-#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
-#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
-#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
-#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
-#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
-#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
+#define S5P_ISP_ARM_LOWPWR 0x1050
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058
+#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110
+#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114
+#define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C
+#define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130
+#define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154
+#define S5P_CMU_RESET_ISP_LOWPWR 0x1174
+#define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190
+#define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194
+#define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198
+#define S5P_OSCCLK_GATE_LOWPWR 0x11A4
+#define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0
+#define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4
+#define S5P_HSI_MEM_LOWPWR 0x11C4
+#define S5P_ROTATOR_MEM_LOWPWR 0x11DC
+#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C
+#define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250
+#define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320
+#define S5P_TOP_ASB_RESET_LOWPWR 0x1344
+#define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348
+#define S5P_ISP_LOWPWR 0x1394
+#define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0
+#define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4
+#define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8
+#define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC
+#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0
+
+#define S5P_ARM_L2_0_OPTION 0x2608
+#define S5P_ARM_L2_1_OPTION 0x2628
+#define S5P_ONENAND_MEM_OPTION 0x2E08
+#define S5P_HSI_MEM_OPTION 0x2E28
+#define S5P_G2D_ACP_MEM_OPTION 0x2E48
+#define S5P_USBOTG_MEM_OPTION 0x2E68
+#define S5P_HSMMC_MEM_OPTION 0x2E88
+#define S5P_CSSYS_MEM_OPTION 0x2EA8
+#define S5P_SECSS_MEM_OPTION 0x2EC8
+#define S5P_ROTATOR_MEM_OPTION 0x2F48
/* Only for EXYNOS4412 */
-#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
-#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
-#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
-#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
-#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
-#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
+#define S5P_ARM_CORE2_LOWPWR 0x1020
+#define S5P_DIS_IRQ_CORE2 0x1024
+#define S5P_DIS_IRQ_CENTRAL2 0x1028
+#define S5P_ARM_CORE3_LOWPWR 0x1030
+#define S5P_DIS_IRQ_CORE3 0x1034
+#define S5P_DIS_IRQ_CENTRAL3 0x1038
/* For EXYNOS5 */
-#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
-#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
+#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
+#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
#define EXYNOS5_SYS_WDTRESET (1 << 20)
-#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
-#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
-#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
-#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
-#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
-#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
-#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
-#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
-#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
-#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
-#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
-#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
-#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
-#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
-#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
-#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
-#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
-#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
-#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
-#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
-#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
-#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
-#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
-#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
-#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
-#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
-#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
-#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
-#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
-#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
-#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
-#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
-#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
-#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
-#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
-#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
-#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
-#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
-#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
-#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
-#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
-#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
-#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
-#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
-#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
-#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
-#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
-#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
-#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
-#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
-#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
-#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
-#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
-#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
-#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
-#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
-#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
-#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
-#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
-#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
-#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
-#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
-#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
-#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
-#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
-#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
-#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
-#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
-#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
-#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
-#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
-#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
-#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
-#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
-#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
-#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
-#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
-#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
-#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
-#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
-#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
-#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
-#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
-#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
-#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
-#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
-#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
-#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
-#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
-#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
-#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
-#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
-#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
-#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
-#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
-#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
-#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
-#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
-#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
-
-#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
-#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
-#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
-#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
-#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
-#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608)
-#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
-#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
-#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
-#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
-#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
-#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
-#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
-#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
-#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
+#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
+#define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
+#define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048
+#define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050
+#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
+#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
+#define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080
+#define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0
+#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
+#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
+#define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C
+#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120
+#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124
+#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C
+#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130
+#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134
+#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138
+#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140
+#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144
+#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148
+#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C
+#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150
+#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154
+#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164
+#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170
+#define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180
+#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184
+#define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188
+#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190
+#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194
+#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198
+#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0
+#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4
+#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0
+#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4
+#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0
+#define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8
+#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC
+#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0
+#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4
+#define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8
+#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC
+#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0
+#define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4
+#define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8
+#define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC
+#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4
+#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
+#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
+#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
+#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208
+#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
+#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
+#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
+#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
+#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
+#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
+#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238
+#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C
+#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240
+#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250
+#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260
+#define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280
+#define EXYNOS5_XXTI_SYS_PWR_REG 0x1284
+#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0
+#define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300
+#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320
+#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340
+#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344
+#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
+#define EXYNOS5_GSCL_SYS_PWR_REG 0x1400
+#define EXYNOS5_ISP_SYS_PWR_REG 0x1404
+#define EXYNOS5_MFC_SYS_PWR_REG 0x1408
+#define EXYNOS5_G3D_SYS_PWR_REG 0x140C
+#define EXYNOS5_DISP1_SYS_PWR_REG 0x1414
+#define EXYNOS5_MAU_SYS_PWR_REG 0x1418
+#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480
+#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484
+#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488
+#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C
+#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494
+#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498
+#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0
+#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4
+#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8
+#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC
+#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4
+#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8
+#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580
+#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584
+#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588
+#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C
+#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594
+#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598
+
+#define EXYNOS5_ARM_CORE0_OPTION 0x2008
+#define EXYNOS5_ARM_CORE1_OPTION 0x2088
+#define EXYNOS5_FSYS_ARM_OPTION 0x2208
+#define EXYNOS5_ISP_ARM_OPTION 0x2288
+#define EXYNOS5_ARM_COMMON_OPTION 0x2408
+#define EXYNOS5_ARM_L2_OPTION 0x2608
+#define EXYNOS5_TOP_PWR_OPTION 0x2C48
+#define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8
+#define EXYNOS5_JPEG_MEM_OPTION 0x2F48
+#define EXYNOS5_GSCL_OPTION 0x4008
+#define EXYNOS5_ISP_OPTION 0x4028
+#define EXYNOS5_MFC_OPTION 0x4048
+#define EXYNOS5_G3D_OPTION 0x4068
+#define EXYNOS5_DISP1_OPTION 0x40A8
+#define EXYNOS5_MAU_OPTION 0x40C8
#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
#define EXYNOS5_USE_SC_COUNTER (1 << 0)
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c186786..f5b9d3f 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -15,7 +15,6 @@
#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
#define S5P_VA_CMU S3C_ADDR(0x02100000)
-#define S5P_VA_PMU S3C_ADDR(0x02180000)
#define S5P_VA_GPIO S3C_ADDR(0x02200000)
#define S5P_VA_GPIO1 S5P_VA_GPIO
#define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v7 2/4] ARM: EXYNOS: Refactored code for using PMU address via DT
@ 2014-07-09 4:00 ` Pankaj Dubey
0 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel
Under "arm/mach-exynos" many files are using PMU register offsets.
Since we have added support for accessing PMU base address via DT,
now we can remove PMU mapping from exynosX_iodesc. Let's convert
all these access using iomapped address.
This will help us in removing static mapping of PMU base address
as well as help in reducing dependency over machine header files.
Thus helping for migration of PMU implementation from machine to
driver folder which can be reused for ARM64 bsed SoC.
Also as we have removed static mappings from "regs-pmu.h" it does
not need map.h anymore. But "platsmp.c" needed this and till now it
got included indirectly. So lets move header inclusion of
"mach/map.h" from "regs-pmu.h" to "platsmp.c".
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/common.h | 14 +-
arch/arm/mach-exynos/exynos.c | 12 +-
arch/arm/mach-exynos/include/mach/map.h | 3 -
arch/arm/mach-exynos/mcpm-exynos.c | 8 +-
arch/arm/mach-exynos/platsmp.c | 4 +-
arch/arm/mach-exynos/pm.c | 76 ++--
arch/arm/mach-exynos/pmu.c | 40 +-
arch/arm/mach-exynos/regs-pmu.h | 522 +++++++++++++-------------
arch/arm/plat-samsung/include/plat/map-s5p.h | 1 -
9 files changed, 339 insertions(+), 341 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f8daa9c..47b904b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -134,7 +134,7 @@ extern void exynos_cpu_die(unsigned int cpu);
/* PMU(Power Management Unit) support */
-#define PMU_TABLE_END NULL
+#define PMU_TABLE_END (-1U)
enum sys_powerdown {
SYS_AFTR,
@@ -144,7 +144,7 @@ enum sys_powerdown {
};
struct exynos_pmu_conf {
- void __iomem *reg;
+ unsigned int offset;
unsigned int val[NUM_SYS_POWERDOWN];
};
@@ -160,4 +160,14 @@ extern void exynos_enter_aftr(void);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
+static inline void pmu_raw_writel(u32 val, u32 offset)
+{
+ __raw_writel(val, pmu_base_addr + offset);
+}
+
+static inline u32 pmu_raw_readl(u32 offset)
+{
+ return __raw_readl(pmu_base_addr + offset);
+}
+
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 173aac8..d75d3e8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -61,11 +61,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = (unsigned long)S5P_VA_PMU,
- .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
- .length = SZ_64K,
- .type = MT_DEVICE,
- }, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
.length = SZ_4K,
@@ -139,11 +134,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
.length = 144 * SZ_1K,
.type = MT_DEVICE,
- }, {
- .virtual = (unsigned long)S5P_VA_PMU,
- .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
- .length = SZ_64K,
- .type = MT_DEVICE,
},
};
@@ -151,7 +141,7 @@ static void exynos_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
u32 val = 0x1;
- void __iomem *addr = EXYNOS_SWRESET;
+ void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
if (of_machine_is_compatible("samsung,exynos5440")) {
u32 status;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 963002f..f0b7e92 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -27,9 +27,6 @@
#define EXYNOS4_PA_SYSCON 0x10010000
#define EXYNOS5_PA_SYSCON 0x10050100
-#define EXYNOS4_PA_PMU 0x10020000
-#define EXYNOS5_PA_PMU 0x10040000
-
#define EXYNOS4_PA_CMU 0x10030000
#define EXYNOS5_PA_CMU 0x10010000
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 9315ba9..70e8ccd 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -55,7 +55,7 @@
"dsb\n\t" \
"ldmfd sp!, {fp, ip}" \
: \
- : "Ir" (S5P_INFORM0) \
+ : "Ir" (pmu_base_addr + S5P_INFORM0) \
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r9", "r10", "lr", "memory")
@@ -337,7 +337,7 @@ static int __init exynos_mcpm_init(void)
* To increase the stability of KFC reset we need to program
* the PMU SPARE3 register
*/
- __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
+ pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
exynos_mcpm_usage_count_init();
@@ -366,11 +366,11 @@ static int __init exynos_mcpm_init(void)
* turned on before the first man is powered up.
*/
for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
- value = __raw_readl(EXYNOS_COMMON_OPTION(i));
+ value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
EXYNOS5420_USE_L2_COMMON_UP_STATE;
- __raw_writel(value, EXYNOS_COMMON_OPTION(i));
+ pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
}
/*
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index cd25a9c..dab0784 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -26,6 +26,8 @@
#include <asm/smp_scu.h>
#include <asm/firmware.h>
+#include <mach/map.h>
+
#include "common.h"
#include "regs-pmu.h"
@@ -34,7 +36,7 @@ extern void exynos4_secondary_startup(void);
static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
- return S5P_INFORM5;
+ return pmu_base_addr + S5P_INFORM5;
return sysram_base_addr;
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index f127c0c..bcb96be 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -111,7 +111,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
*/
void exynos_cpu_power_down(int cpu)
{
- __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+ pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@@ -122,8 +122,8 @@ void exynos_cpu_power_down(int cpu)
*/
void exynos_cpu_power_up(int cpu)
{
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
- EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+ pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@@ -133,7 +133,7 @@ void exynos_cpu_power_up(int cpu)
*/
int exynos_cpu_power_state(int cpu)
{
- return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+ return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
S5P_CORE_LOCAL_PWR_EN);
}
@@ -143,7 +143,7 @@ int exynos_cpu_power_state(int cpu)
*/
void exynos_cluster_power_down(int cluster)
{
- __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
+ pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
}
/**
@@ -152,8 +152,8 @@ void exynos_cluster_power_down(int cluster)
*/
void exynos_cluster_power_up(int cluster)
{
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
- EXYNOS_COMMON_CONFIGURATION(cluster));
+ pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ EXYNOS_COMMON_CONFIGURATION(cluster));
}
/**
@@ -163,16 +163,20 @@ void exynos_cluster_power_up(int cluster)
*/
int exynos_cluster_power_state(int cluster)
{
- return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
+ return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
S5P_CORE_LOCAL_PWR_EN);
}
#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
- (sysram_base_addr + 0x24) : S5P_INFORM0))
+ pmu_base_addr + S5P_INFORM7 : \
+ (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+ (sysram_base_addr + 0x24) : \
+ pmu_base_addr + S5P_INFORM0))
#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
- (sysram_base_addr + 0x20) : S5P_INFORM1))
+ pmu_base_addr + S5P_INFORM6 : \
+ (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+ (sysram_base_addr + 0x20) : \
+ pmu_base_addr + S5P_INFORM1))
#define S5P_CHECK_AFTR 0xFCBA0D10
#define S5P_CHECK_SLEEP 0x00000BAD
@@ -180,7 +184,7 @@ int exynos_cluster_power_state(int cluster)
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos_set_wakeupmask(long mask)
{
- __raw_writel(mask, S5P_WAKEUP_MASK);
+ pmu_raw_writel(mask, S5P_WAKEUP_MASK);
}
static void exynos_cpu_set_boot_vector(long flags)
@@ -257,27 +261,27 @@ static void exynos_pm_prepare(void)
unsigned int tmp;
/* Set wake-up mask registers */
- __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
- __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+ pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+ pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
if (soc_is_exynos5250()) {
s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
- tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+ tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
- __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+ pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
/* Set value of power down register for sleep mode */
exynos_sys_powerdown_conf(SYS_SLEEP);
- __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
+ pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure@least INFORM0 has the resume address */
- __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+ pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
static void exynos_pm_central_suspend(void)
@@ -285,9 +289,9 @@ static void exynos_pm_central_suspend(void)
unsigned long tmp;
/* Setting Central Sequence Register for power down mode */
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}
static int exynos_pm_suspend(void)
@@ -299,7 +303,7 @@ static int exynos_pm_suspend(void)
/* Setting SEQ_OPTION register */
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
- __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_save_register();
@@ -317,12 +321,12 @@ static int exynos_pm_central_resume(void)
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* clear the wakeup state register */
- __raw_writel(0x0, S5P_WAKEUP_STAT);
+ pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
return -1;
}
@@ -340,13 +344,13 @@ static void exynos_pm_resume(void)
/* For release retention */
- __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+ pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
if (soc_is_exynos5250())
s3c_pm_do_restore(exynos5_sys_save,
@@ -360,7 +364,7 @@ static void exynos_pm_resume(void)
early_wakeup:
/* Clear SLEEP mode set in INFORM1 */
- __raw_writel(0x0, S5P_INFORM1);
+ pmu_raw_writel(0x0, S5P_INFORM1);
return;
}
@@ -404,7 +408,7 @@ static int exynos_suspend_enter(suspend_state_t state)
s3c_pm_restore_uarts();
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
- __raw_readl(S5P_WAKEUP_STAT));
+ pmu_raw_readl(S5P_WAKEUP_STAT));
s3c_pm_check_restore();
@@ -475,9 +479,9 @@ void __init exynos_pm_init(void)
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
/* All wakeup disable */
- tmp = __raw_readl(S5P_WAKEUP_MASK);
+ tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
- __raw_writel(tmp, S5P_WAKEUP_MASK);
+ pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
register_syscore_ops(&exynos_pm_syscore_ops);
suspend_set_ops(&exynos_suspend_ops);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index dcfcb44..ff9d23f 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -18,7 +18,7 @@
static const struct exynos_pmu_conf *exynos_pmu_config;
static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
- /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+ /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@@ -212,7 +212,7 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
};
static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
- /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+ /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
@@ -315,7 +315,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
};
-static void __iomem * const exynos5_list_both_cnt_feed[] = {
+static unsigned int const exynos5_list_both_cnt_feed[] = {
EXYNOS5_ARM_CORE0_OPTION,
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_ARM_COMMON_OPTION,
@@ -329,7 +329,7 @@ static void __iomem * const exynos5_list_both_cnt_feed[] = {
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
};
-static void __iomem * const exynos5_list_diable_wfi_wfe[] = {
+static unsigned int const exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_FSYS_ARM_OPTION,
EXYNOS5_ISP_ARM_OPTION,
@@ -344,27 +344,27 @@ static void exynos5_init_pmu(void)
* Enable both SC_FEEDBACK and SC_COUNTER
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
- tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
+ tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
EXYNOS5_USE_SC_COUNTER);
- __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
+ pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
}
/*
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
*/
- tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
+ tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
- __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
+ pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
/*
* Disable WFI/WFE on XXX_OPTION
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
- tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
+ tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
EXYNOS5_OPTION_USE_STANDBYWFI);
- __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
+ pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
}
}
@@ -375,14 +375,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
if (soc_is_exynos5250())
exynos5_init_pmu();
- for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
- __raw_writel(exynos_pmu_config[i].val[mode],
- exynos_pmu_config[i].reg);
+ for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
+ pmu_raw_writel(exynos_pmu_config[i].val[mode],
+ exynos_pmu_config[i].offset);
if (soc_is_exynos4412()) {
- for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
- __raw_writel(exynos4412_pmu_config[i].val[mode],
- exynos4412_pmu_config[i].reg);
+ for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
+ pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
+ exynos4412_pmu_config[i].offset);
}
}
@@ -403,13 +403,13 @@ static int __init exynos_pmu_init(void)
* When SYS_WDTRESET is set, watchdog timer reset request
* is ignored by power management unit.
*/
- value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+ value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
value &= ~EXYNOS5_SYS_WDTRESET;
- __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+ pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
- value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+ value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
value &= ~EXYNOS5_SYS_WDTRESET;
- __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+ pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index e5e298c..96a1569 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -12,106 +12,102 @@
#ifndef __ASM_ARCH_REGS_PMU_H
#define __ASM_ARCH_REGS_PMU_H __FILE__
-#include <mach/map.h>
-
-#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
-
-#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
+#define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
-#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
+#define S5P_CENTRAL_SEQ_OPTION 0x0208
#define S5P_USE_STANDBY_WFI0 (1 << 16)
#define S5P_USE_STANDBY_WFE0 (1 << 24)
-#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
-#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
-
-#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
-#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
-#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
-
-#define S5P_INFORM0 S5P_PMUREG(0x0800)
-#define S5P_INFORM1 S5P_PMUREG(0x0804)
-#define S5P_INFORM5 S5P_PMUREG(0x0814)
-#define S5P_INFORM6 S5P_PMUREG(0x0818)
-#define S5P_INFORM7 S5P_PMUREG(0x081C)
-#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C)
-
-#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
-#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
-#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
-#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
-#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
-#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
-#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
-#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
-#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
-#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
-#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
-#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
-#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
-#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
-#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
-#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
-#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
-#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
-#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
-#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
-#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
-#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
-#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
-#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
-#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
-#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
-#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
-#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
-#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
-#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
-#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
-#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
-#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
-#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
-#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
-#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
-#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
-#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
-#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
-#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
-#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
-#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
-#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
-#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
-#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
-#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
-#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
-#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
-#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
-#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
-#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
-#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
-#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
-#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
-#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
-#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
-#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
-#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
-#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
-#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
-#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
-#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
-#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
-
-#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
+#define EXYNOS_SWRESET 0x0400
+#define EXYNOS5440_SWRESET 0x00C4
+
+#define S5P_WAKEUP_STAT 0x0600
+#define S5P_EINT_WAKEUP_MASK 0x0604
+#define S5P_WAKEUP_MASK 0x0608
+
+#define S5P_INFORM0 0x0800
+#define S5P_INFORM1 0x0804
+#define S5P_INFORM5 0x0814
+#define S5P_INFORM6 0x0818
+#define S5P_INFORM7 0x081C
+#define S5P_PMU_SPARE3 0x090C
+
+#define S5P_ARM_CORE0_LOWPWR 0x1000
+#define S5P_DIS_IRQ_CORE0 0x1004
+#define S5P_DIS_IRQ_CENTRAL0 0x1008
+#define S5P_ARM_CORE1_LOWPWR 0x1010
+#define S5P_DIS_IRQ_CORE1 0x1014
+#define S5P_DIS_IRQ_CENTRAL1 0x1018
+#define S5P_ARM_COMMON_LOWPWR 0x1080
+#define S5P_L2_0_LOWPWR 0x10C0
+#define S5P_L2_1_LOWPWR 0x10C4
+#define S5P_CMU_ACLKSTOP_LOWPWR 0x1100
+#define S5P_CMU_SCLKSTOP_LOWPWR 0x1104
+#define S5P_CMU_RESET_LOWPWR 0x110C
+#define S5P_APLL_SYSCLK_LOWPWR 0x1120
+#define S5P_MPLL_SYSCLK_LOWPWR 0x1124
+#define S5P_VPLL_SYSCLK_LOWPWR 0x1128
+#define S5P_EPLL_SYSCLK_LOWPWR 0x112C
+#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138
+#define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C
+#define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140
+#define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144
+#define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148
+#define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C
+#define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150
+#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158
+#define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C
+#define S5P_CMU_RESET_CAM_LOWPWR 0x1160
+#define S5P_CMU_RESET_TV_LOWPWR 0x1164
+#define S5P_CMU_RESET_MFC_LOWPWR 0x1168
+#define S5P_CMU_RESET_G3D_LOWPWR 0x116C
+#define S5P_CMU_RESET_LCD0_LOWPWR 0x1170
+#define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178
+#define S5P_CMU_RESET_GPS_LOWPWR 0x117C
+#define S5P_TOP_BUS_LOWPWR 0x1180
+#define S5P_TOP_RETENTION_LOWPWR 0x1184
+#define S5P_TOP_PWR_LOWPWR 0x1188
+#define S5P_LOGIC_RESET_LOWPWR 0x11A0
+#define S5P_ONENAND_MEM_LOWPWR 0x11C0
+#define S5P_G2D_ACP_MEM_LOWPWR 0x11C8
+#define S5P_USBOTG_MEM_LOWPWR 0x11CC
+#define S5P_HSMMC_MEM_LOWPWR 0x11D0
+#define S5P_CSSYS_MEM_LOWPWR 0x11D4
+#define S5P_SECSS_MEM_LOWPWR 0x11D8
+#define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200
+#define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204
+#define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220
+#define S5P_PAD_RETENTION_UART_LOWPWR 0x1224
+#define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228
+#define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C
+#define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230
+#define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234
+#define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240
+#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260
+#define S5P_XUSBXTI_LOWPWR 0x1280
+#define S5P_XXTI_LOWPWR 0x1284
+#define S5P_EXT_REGULATOR_LOWPWR 0x12C0
+#define S5P_GPIO_MODE_LOWPWR 0x1300
+#define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340
+#define S5P_CAM_LOWPWR 0x1380
+#define S5P_TV_LOWPWR 0x1384
+#define S5P_MFC_LOWPWR 0x1388
+#define S5P_G3D_LOWPWR 0x138C
+#define S5P_LCD0_LOWPWR 0x1390
+#define S5P_MAUDIO_LOWPWR 0x1398
+#define S5P_GPS_LOWPWR 0x139C
+#define S5P_GPS_ALIVE_LOWPWR 0x13A0
+
+#define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000
#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
(EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
#define EXYNOS_ARM_CORE_STATUS(_nr) \
(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
-#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500)
+#define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500
#define EXYNOS_COMMON_CONFIGURATION(_nr) \
(EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
#define EXYNOS_COMMON_STATUS(_nr) \
@@ -119,195 +115,195 @@
#define EXYNOS_COMMON_OPTION(_nr) \
(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
-#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
-#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
-#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
-#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
-#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
-#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
-#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
+#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
+#define S5P_PAD_RET_GPIO_OPTION 0x3108
+#define S5P_PAD_RET_UART_OPTION 0x3128
+#define S5P_PAD_RET_MMCA_OPTION 0x3148
+#define S5P_PAD_RET_MMCB_OPTION 0x3168
+#define S5P_PAD_RET_EBIA_OPTION 0x3188
+#define S5P_PAD_RET_EBIB_OPTION 0x31A8
#define S5P_CORE_LOCAL_PWR_EN 0x3
/* Only for EXYNOS4210 */
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
-#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
-#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
-#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
+#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
+#define S5P_MODIMIF_MEM_LOWPWR 0x11C4
+#define S5P_PCIE_MEM_LOWPWR 0x11E0
+#define S5P_SATA_MEM_LOWPWR 0x11E4
+#define S5P_LCD1_LOWPWR 0x1394
/* Only for EXYNOS4x12 */
-#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
-#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
-#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
-#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
-#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
-#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
-#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
-#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
-#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
-#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
-#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
-#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
-#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
-#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
-#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
-#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
-#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
-#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
-#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
-#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
-#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
-#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
-#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
-#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
-#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
-#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
-#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
-
-#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
-#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
-#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
-#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
-#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
-#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
-#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
-#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
-#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
-#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
+#define S5P_ISP_ARM_LOWPWR 0x1050
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058
+#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110
+#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114
+#define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C
+#define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130
+#define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154
+#define S5P_CMU_RESET_ISP_LOWPWR 0x1174
+#define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190
+#define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194
+#define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198
+#define S5P_OSCCLK_GATE_LOWPWR 0x11A4
+#define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0
+#define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4
+#define S5P_HSI_MEM_LOWPWR 0x11C4
+#define S5P_ROTATOR_MEM_LOWPWR 0x11DC
+#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C
+#define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250
+#define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320
+#define S5P_TOP_ASB_RESET_LOWPWR 0x1344
+#define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348
+#define S5P_ISP_LOWPWR 0x1394
+#define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0
+#define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4
+#define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8
+#define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC
+#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0
+
+#define S5P_ARM_L2_0_OPTION 0x2608
+#define S5P_ARM_L2_1_OPTION 0x2628
+#define S5P_ONENAND_MEM_OPTION 0x2E08
+#define S5P_HSI_MEM_OPTION 0x2E28
+#define S5P_G2D_ACP_MEM_OPTION 0x2E48
+#define S5P_USBOTG_MEM_OPTION 0x2E68
+#define S5P_HSMMC_MEM_OPTION 0x2E88
+#define S5P_CSSYS_MEM_OPTION 0x2EA8
+#define S5P_SECSS_MEM_OPTION 0x2EC8
+#define S5P_ROTATOR_MEM_OPTION 0x2F48
/* Only for EXYNOS4412 */
-#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
-#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
-#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
-#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
-#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
-#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
+#define S5P_ARM_CORE2_LOWPWR 0x1020
+#define S5P_DIS_IRQ_CORE2 0x1024
+#define S5P_DIS_IRQ_CENTRAL2 0x1028
+#define S5P_ARM_CORE3_LOWPWR 0x1030
+#define S5P_DIS_IRQ_CORE3 0x1034
+#define S5P_DIS_IRQ_CENTRAL3 0x1038
/* For EXYNOS5 */
-#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
-#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
+#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
+#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
#define EXYNOS5_SYS_WDTRESET (1 << 20)
-#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
-#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
-#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
-#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
-#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
-#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
-#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
-#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
-#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
-#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
-#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
-#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
-#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
-#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
-#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
-#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
-#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
-#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
-#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
-#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
-#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
-#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
-#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
-#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
-#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
-#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
-#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
-#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
-#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
-#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
-#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
-#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
-#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
-#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
-#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
-#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
-#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
-#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
-#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
-#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
-#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
-#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
-#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
-#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
-#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
-#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
-#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
-#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
-#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
-#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
-#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
-#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
-#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
-#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
-#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
-#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
-#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
-#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
-#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
-#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
-#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
-#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
-#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
-#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
-#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
-#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
-#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
-#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
-#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
-#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
-#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
-#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
-#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
-#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
-#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
-#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
-#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
-#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
-#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
-#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
-#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
-#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
-#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
-#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
-#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
-#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
-#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
-#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
-#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
-#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
-#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
-#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
-#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
-#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
-#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
-#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
-#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
-#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
-#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
-
-#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
-#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
-#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
-#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
-#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
-#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608)
-#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
-#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
-#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
-#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
-#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
-#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
-#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
-#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
-#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
+#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
+#define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
+#define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048
+#define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050
+#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
+#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
+#define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080
+#define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0
+#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
+#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
+#define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C
+#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120
+#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124
+#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C
+#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130
+#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134
+#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138
+#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140
+#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144
+#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148
+#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C
+#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150
+#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154
+#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164
+#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170
+#define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180
+#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184
+#define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188
+#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190
+#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194
+#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198
+#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0
+#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4
+#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0
+#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4
+#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0
+#define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8
+#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC
+#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0
+#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4
+#define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8
+#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC
+#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0
+#define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4
+#define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8
+#define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC
+#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4
+#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
+#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
+#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
+#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208
+#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
+#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
+#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
+#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
+#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
+#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
+#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238
+#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C
+#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240
+#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250
+#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260
+#define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280
+#define EXYNOS5_XXTI_SYS_PWR_REG 0x1284
+#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0
+#define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300
+#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320
+#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340
+#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344
+#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
+#define EXYNOS5_GSCL_SYS_PWR_REG 0x1400
+#define EXYNOS5_ISP_SYS_PWR_REG 0x1404
+#define EXYNOS5_MFC_SYS_PWR_REG 0x1408
+#define EXYNOS5_G3D_SYS_PWR_REG 0x140C
+#define EXYNOS5_DISP1_SYS_PWR_REG 0x1414
+#define EXYNOS5_MAU_SYS_PWR_REG 0x1418
+#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480
+#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484
+#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488
+#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C
+#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494
+#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498
+#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0
+#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4
+#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8
+#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC
+#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4
+#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8
+#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580
+#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584
+#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588
+#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C
+#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594
+#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598
+
+#define EXYNOS5_ARM_CORE0_OPTION 0x2008
+#define EXYNOS5_ARM_CORE1_OPTION 0x2088
+#define EXYNOS5_FSYS_ARM_OPTION 0x2208
+#define EXYNOS5_ISP_ARM_OPTION 0x2288
+#define EXYNOS5_ARM_COMMON_OPTION 0x2408
+#define EXYNOS5_ARM_L2_OPTION 0x2608
+#define EXYNOS5_TOP_PWR_OPTION 0x2C48
+#define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8
+#define EXYNOS5_JPEG_MEM_OPTION 0x2F48
+#define EXYNOS5_GSCL_OPTION 0x4008
+#define EXYNOS5_ISP_OPTION 0x4028
+#define EXYNOS5_MFC_OPTION 0x4048
+#define EXYNOS5_G3D_OPTION 0x4068
+#define EXYNOS5_DISP1_OPTION 0x40A8
+#define EXYNOS5_MAU_OPTION 0x40C8
#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
#define EXYNOS5_USE_SC_COUNTER (1 << 0)
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c186786..f5b9d3f 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -15,7 +15,6 @@
#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
#define S5P_VA_CMU S3C_ADDR(0x02100000)
-#define S5P_VA_PMU S3C_ADDR(0x02180000)
#define S5P_VA_GPIO S3C_ADDR(0x02200000)
#define S5P_VA_GPIO1 S5P_VA_GPIO
#define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
2014-07-09 4:00 ` Pankaj Dubey
@ 2014-07-09 4:00 ` Pankaj Dubey
-1 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: kgene.kim, linux, t.figa, vikas.sajjan, joshi, naushad,
thomas.ab, chow.kim, Pankaj Dubey
This patch modifies Exynos Power Management Unit (PMU) initialization
implementation in following way:
- Added platform driver support and probe function where Exynos PMU
driver will register itself as syscon provider with syscon framework.
- Added platform struct exynos_pmu_data to hold platform specific data.
- For each SoC's PMU support now we can add platform data and statically
bind PMU configuration and SoC specific initialization function.
- Separate each SoC's PMU initialization function and make it as part of
platform data.
- It also removes uses of soc_is_exynosXYZ().
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/pmu.c | 185 +++++++++++++++++++++++++++++++++---------
2 files changed, 146 insertions(+), 40 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 8f9b66c..a2944ac 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -24,6 +24,7 @@ menuconfig ARCH_EXYNOS
select PM_GENERIC_DOMAINS if PM_RUNTIME
select S5P_DEV_MFC
select SRAM
+ select MFD_SYSCON
help
Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index ff9d23f..5b76728 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS - CPU PMU(Power Management Unit) support
@@ -10,12 +10,28 @@
*/
#include <linux/io.h>
-#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
#include "common.h"
#include "regs-pmu.h"
-static const struct exynos_pmu_conf *exynos_pmu_config;
+struct exynos_pmu_data {
+ const struct exynos_pmu_conf *pmu_config;
+ const struct exynos_pmu_conf *pmu_config_extra;
+
+ void (*pmu_init)(void);
+ void (*powerdown_conf)(enum sys_powerdown);
+};
+
+struct exynos_pmu_context {
+ struct device *dev;
+ const struct exynos_pmu_data *pmu_data;
+};
+
+static struct exynos_pmu_context *pmu_context;
static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
@@ -335,7 +351,7 @@ static unsigned int const exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ISP_ARM_OPTION,
};
-static void exynos5_init_pmu(void)
+static void exynos5_powerdown_conf(enum sys_powerdown mode)
{
unsigned int i;
unsigned int tmp;
@@ -372,51 +388,140 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int i;
- if (soc_is_exynos5250())
- exynos5_init_pmu();
+ const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
- for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
- pmu_raw_writel(exynos_pmu_config[i].val[mode],
- exynos_pmu_config[i].offset);
+ if (pmu_data->powerdown_conf)
+ pmu_data->powerdown_conf(mode);
- if (soc_is_exynos4412()) {
- for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
- pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
- exynos4412_pmu_config[i].offset);
+ if (pmu_data->pmu_config) {
+ for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END) ; i++)
+ pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
+ pmu_data->pmu_config[i].offset);
+ }
+
+ if (pmu_data->pmu_config_extra) {
+ for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
+ pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
+ pmu_data->pmu_config_extra[i].offset);
}
}
-static int __init exynos_pmu_init(void)
+static void exynos5250_pmu_init(void)
{
unsigned int value;
+ /*
+ * When SYS_WDTRESET is set, watchdog timer reset request
+ * is ignored by power management unit.
+ */
+ value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+ value &= ~EXYNOS5_SYS_WDTRESET;
+ pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+
+ value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+ value &= ~EXYNOS5_SYS_WDTRESET;
+ pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+}
+
+static const struct exynos_pmu_data exynos4210_pmu_data = {
+ .pmu_config = exynos4210_pmu_config,
+};
+
+static const struct exynos_pmu_data exynos4212_pmu_data = {
+ .pmu_config = exynos4x12_pmu_config,
+};
+
+static const struct exynos_pmu_data exynos4412_pmu_data = {
+ .pmu_config = exynos4x12_pmu_config,
+ .pmu_config_extra = exynos4412_pmu_config,
+};
+
+static const struct exynos_pmu_data exynos5250_pmu_data = {
+ .pmu_config = exynos5250_pmu_config,
+ .pmu_init = exynos5250_pmu_init,
+ .powerdown_conf = exynos5_powerdown_conf,
+};
+
+static const struct regmap_config pmu_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
- exynos_pmu_config = exynos4210_pmu_config;
-
- if (soc_is_exynos4210()) {
- exynos_pmu_config = exynos4210_pmu_config;
- pr_info("EXYNOS4210 PMU Initialize\n");
- } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
- exynos_pmu_config = exynos4x12_pmu_config;
- pr_info("EXYNOS4x12 PMU Initialize\n");
- } else if (soc_is_exynos5250()) {
- /*
- * When SYS_WDTRESET is set, watchdog timer reset request
- * is ignored by power management unit.
- */
- value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
- value &= ~EXYNOS5_SYS_WDTRESET;
- pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
-
- value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
- value &= ~EXYNOS5_SYS_WDTRESET;
- pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
-
- exynos_pmu_config = exynos5250_pmu_config;
- pr_info("EXYNOS5250 PMU Initialize\n");
- } else {
- pr_info("EXYNOS: PMU not supported\n");
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static const struct of_device_id exynos_pmu_of_device_ids[] = {
+ {
+ .compatible = "samsung,exynos4210-pmu",
+ .data = &exynos4210_pmu_data,
+ }, {
+ .compatible = "samsung,exynos4212-pmu",
+ .data = &exynos4212_pmu_data,
+ }, {
+ .compatible = "samsung,exynos4412-pmu",
+ .data = &exynos4412_pmu_data,
+ }, {
+ .compatible = "samsung,exynos5250-pmu",
+ .data = &exynos5250_pmu_data,
+ },
+ { /*sentinel*/ },
+};
+
+static int exynos_pmu_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pmu_base_addr = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pmu_base_addr))
+ return PTR_ERR(pmu_base_addr);
+
+ pmu_context = devm_kzalloc(&pdev->dev,
+ sizeof(struct exynos_pmu_context),
+ GFP_KERNEL);
+ if (!pmu_context) {
+ dev_err(dev, "Cannot allocate memory.\n");
+ return -ENOMEM;
+ }
+ pmu_context->dev = dev;
+
+ regmap = devm_regmap_init_mmio(dev, pmu_base_addr,
+ &pmu_regmap_config);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "regmap init failed\n");
+ return PTR_ERR(regmap);
}
+ devm_syscon_register(dev, regmap);
+
+ match = of_match_node(exynos_pmu_of_device_ids, pdev->dev.of_node);
+
+ pmu_context->pmu_data = match->data;
+
+ if (pmu_context->pmu_data->pmu_init)
+ pmu_context->pmu_data->pmu_init();
+
+ platform_set_drvdata(pdev, pmu_context);
+
+ dev_dbg(dev, "Exynos PMU Driver probe done\n");
return 0;
}
-arch_initcall(exynos_pmu_init);
+
+static struct platform_driver exynos_pmu_driver = {
+ .driver = {
+ .name = "exynos-pmu",
+ .owner = THIS_MODULE,
+ .of_match_table = exynos_pmu_of_device_ids,
+ },
+ .probe = exynos_pmu_probe,
+};
+
+static int __init exynos_pmu_init(void)
+{
+ return platform_driver_register(&exynos_pmu_driver);
+
+}
+postcore_initcall(exynos_pmu_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
@ 2014-07-09 4:00 ` Pankaj Dubey
0 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel
This patch modifies Exynos Power Management Unit (PMU) initialization
implementation in following way:
- Added platform driver support and probe function where Exynos PMU
driver will register itself as syscon provider with syscon framework.
- Added platform struct exynos_pmu_data to hold platform specific data.
- For each SoC's PMU support now we can add platform data and statically
bind PMU configuration and SoC specific initialization function.
- Separate each SoC's PMU initialization function and make it as part of
platform data.
- It also removes uses of soc_is_exynosXYZ().
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/pmu.c | 185 +++++++++++++++++++++++++++++++++---------
2 files changed, 146 insertions(+), 40 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 8f9b66c..a2944ac 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -24,6 +24,7 @@ menuconfig ARCH_EXYNOS
select PM_GENERIC_DOMAINS if PM_RUNTIME
select S5P_DEV_MFC
select SRAM
+ select MFD_SYSCON
help
Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index ff9d23f..5b76728 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS - CPU PMU(Power Management Unit) support
@@ -10,12 +10,28 @@
*/
#include <linux/io.h>
-#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
#include "common.h"
#include "regs-pmu.h"
-static const struct exynos_pmu_conf *exynos_pmu_config;
+struct exynos_pmu_data {
+ const struct exynos_pmu_conf *pmu_config;
+ const struct exynos_pmu_conf *pmu_config_extra;
+
+ void (*pmu_init)(void);
+ void (*powerdown_conf)(enum sys_powerdown);
+};
+
+struct exynos_pmu_context {
+ struct device *dev;
+ const struct exynos_pmu_data *pmu_data;
+};
+
+static struct exynos_pmu_context *pmu_context;
static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
@@ -335,7 +351,7 @@ static unsigned int const exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ISP_ARM_OPTION,
};
-static void exynos5_init_pmu(void)
+static void exynos5_powerdown_conf(enum sys_powerdown mode)
{
unsigned int i;
unsigned int tmp;
@@ -372,51 +388,140 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int i;
- if (soc_is_exynos5250())
- exynos5_init_pmu();
+ const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
- for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
- pmu_raw_writel(exynos_pmu_config[i].val[mode],
- exynos_pmu_config[i].offset);
+ if (pmu_data->powerdown_conf)
+ pmu_data->powerdown_conf(mode);
- if (soc_is_exynos4412()) {
- for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
- pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
- exynos4412_pmu_config[i].offset);
+ if (pmu_data->pmu_config) {
+ for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END) ; i++)
+ pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
+ pmu_data->pmu_config[i].offset);
+ }
+
+ if (pmu_data->pmu_config_extra) {
+ for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
+ pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
+ pmu_data->pmu_config_extra[i].offset);
}
}
-static int __init exynos_pmu_init(void)
+static void exynos5250_pmu_init(void)
{
unsigned int value;
+ /*
+ * When SYS_WDTRESET is set, watchdog timer reset request
+ * is ignored by power management unit.
+ */
+ value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+ value &= ~EXYNOS5_SYS_WDTRESET;
+ pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+
+ value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+ value &= ~EXYNOS5_SYS_WDTRESET;
+ pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+}
+
+static const struct exynos_pmu_data exynos4210_pmu_data = {
+ .pmu_config = exynos4210_pmu_config,
+};
+
+static const struct exynos_pmu_data exynos4212_pmu_data = {
+ .pmu_config = exynos4x12_pmu_config,
+};
+
+static const struct exynos_pmu_data exynos4412_pmu_data = {
+ .pmu_config = exynos4x12_pmu_config,
+ .pmu_config_extra = exynos4412_pmu_config,
+};
+
+static const struct exynos_pmu_data exynos5250_pmu_data = {
+ .pmu_config = exynos5250_pmu_config,
+ .pmu_init = exynos5250_pmu_init,
+ .powerdown_conf = exynos5_powerdown_conf,
+};
+
+static const struct regmap_config pmu_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
- exynos_pmu_config = exynos4210_pmu_config;
-
- if (soc_is_exynos4210()) {
- exynos_pmu_config = exynos4210_pmu_config;
- pr_info("EXYNOS4210 PMU Initialize\n");
- } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
- exynos_pmu_config = exynos4x12_pmu_config;
- pr_info("EXYNOS4x12 PMU Initialize\n");
- } else if (soc_is_exynos5250()) {
- /*
- * When SYS_WDTRESET is set, watchdog timer reset request
- * is ignored by power management unit.
- */
- value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
- value &= ~EXYNOS5_SYS_WDTRESET;
- pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
-
- value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
- value &= ~EXYNOS5_SYS_WDTRESET;
- pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
-
- exynos_pmu_config = exynos5250_pmu_config;
- pr_info("EXYNOS5250 PMU Initialize\n");
- } else {
- pr_info("EXYNOS: PMU not supported\n");
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static const struct of_device_id exynos_pmu_of_device_ids[] = {
+ {
+ .compatible = "samsung,exynos4210-pmu",
+ .data = &exynos4210_pmu_data,
+ }, {
+ .compatible = "samsung,exynos4212-pmu",
+ .data = &exynos4212_pmu_data,
+ }, {
+ .compatible = "samsung,exynos4412-pmu",
+ .data = &exynos4412_pmu_data,
+ }, {
+ .compatible = "samsung,exynos5250-pmu",
+ .data = &exynos5250_pmu_data,
+ },
+ { /*sentinel*/ },
+};
+
+static int exynos_pmu_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pmu_base_addr = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pmu_base_addr))
+ return PTR_ERR(pmu_base_addr);
+
+ pmu_context = devm_kzalloc(&pdev->dev,
+ sizeof(struct exynos_pmu_context),
+ GFP_KERNEL);
+ if (!pmu_context) {
+ dev_err(dev, "Cannot allocate memory.\n");
+ return -ENOMEM;
+ }
+ pmu_context->dev = dev;
+
+ regmap = devm_regmap_init_mmio(dev, pmu_base_addr,
+ &pmu_regmap_config);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "regmap init failed\n");
+ return PTR_ERR(regmap);
}
+ devm_syscon_register(dev, regmap);
+
+ match = of_match_node(exynos_pmu_of_device_ids, pdev->dev.of_node);
+
+ pmu_context->pmu_data = match->data;
+
+ if (pmu_context->pmu_data->pmu_init)
+ pmu_context->pmu_data->pmu_init();
+
+ platform_set_drvdata(pdev, pmu_context);
+
+ dev_dbg(dev, "Exynos PMU Driver probe done\n");
return 0;
}
-arch_initcall(exynos_pmu_init);
+
+static struct platform_driver exynos_pmu_driver = {
+ .driver = {
+ .name = "exynos-pmu",
+ .owner = THIS_MODULE,
+ .of_match_table = exynos_pmu_of_device_ids,
+ },
+ .probe = exynos_pmu_probe,
+};
+
+static int __init exynos_pmu_init(void)
+{
+ return platform_driver_register(&exynos_pmu_driver);
+
+}
+postcore_initcall(exynos_pmu_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v7 4/4] ARM: EXYNOS: Move PMU specific definitions from common.h
2014-07-09 4:00 ` Pankaj Dubey
@ 2014-07-09 4:00 ` Pankaj Dubey
-1 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: kgene.kim, linux, t.figa, vikas.sajjan, joshi, naushad,
thomas.ab, chow.kim, Pankaj Dubey
This patch moves PMU specific definitions into a new file
as exynos-pmu.h.
This will help in reducing dependency of common.h in pmu.c.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/common.h | 17 -----------------
arch/arm/mach-exynos/exynos-pmu.h | 24 ++++++++++++++++++++++++
arch/arm/mach-exynos/pm.c | 1 +
arch/arm/mach-exynos/pmu.c | 20 +++++++++++++++++++-
4 files changed, 44 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/mach-exynos/exynos-pmu.h
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 47b904b..9019d86 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -132,23 +132,6 @@ extern struct smp_operations exynos_smp_ops;
extern void exynos_cpu_die(unsigned int cpu);
-/* PMU(Power Management Unit) support */
-
-#define PMU_TABLE_END (-1U)
-
-enum sys_powerdown {
- SYS_AFTR,
- SYS_LPA,
- SYS_SLEEP,
- NUM_SYS_POWERDOWN,
-};
-
-struct exynos_pmu_conf {
- unsigned int offset;
- unsigned int val[NUM_SYS_POWERDOWN];
-};
-
-extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
extern void exynos_cpu_power_down(int cpu);
extern void exynos_cpu_power_up(int cpu);
extern int exynos_cpu_power_state(int cpu);
diff --git a/arch/arm/mach-exynos/exynos-pmu.h b/arch/arm/mach-exynos/exynos-pmu.h
new file mode 100644
index 0000000..a2ab0d5
--- /dev/null
+++ b/arch/arm/mach-exynos/exynos-pmu.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Header for EXYNOS PMU Driver support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __EXYNOS_PMU_H
+#define __EXYNOS_PMU_H
+
+enum sys_powerdown {
+ SYS_AFTR,
+ SYS_LPA,
+ SYS_SLEEP,
+ NUM_SYS_POWERDOWN,
+};
+
+extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+
+#endif /* __EXYNOS_PMU_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index bcb96be..b2efe8c 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -34,6 +34,7 @@
#include <mach/map.h>
#include "common.h"
+#include "exynos-pmu.h"
#include "regs-pmu.h"
#include "regs-sys.h"
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 5b76728..117f333 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -15,9 +15,16 @@
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
-#include "common.h"
+#include "exynos-pmu.h"
#include "regs-pmu.h"
+#define PMU_TABLE_END (-1U)
+
+struct exynos_pmu_conf {
+ unsigned int offset;
+ unsigned int val[NUM_SYS_POWERDOWN];
+};
+
struct exynos_pmu_data {
const struct exynos_pmu_conf *pmu_config;
const struct exynos_pmu_conf *pmu_config_extra;
@@ -31,8 +38,19 @@ struct exynos_pmu_context {
const struct exynos_pmu_data *pmu_data;
};
+static void __iomem *pmu_base_addr;
static struct exynos_pmu_context *pmu_context;
+static inline void pmu_raw_writel(u32 val, u32 offset)
+{
+ __raw_writel(val, pmu_base_addr + offset);
+}
+
+static inline u32 pmu_raw_readl(u32 offset)
+{
+ return __raw_readl(pmu_base_addr + offset);
+}
+
static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
--
1.7.9.5
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v7 4/4] ARM: EXYNOS: Move PMU specific definitions from common.h
@ 2014-07-09 4:00 ` Pankaj Dubey
0 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-09 4:00 UTC (permalink / raw)
To: linux-arm-kernel
This patch moves PMU specific definitions into a new file
as exynos-pmu.h.
This will help in reducing dependency of common.h in pmu.c.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/common.h | 17 -----------------
arch/arm/mach-exynos/exynos-pmu.h | 24 ++++++++++++++++++++++++
arch/arm/mach-exynos/pm.c | 1 +
arch/arm/mach-exynos/pmu.c | 20 +++++++++++++++++++-
4 files changed, 44 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/mach-exynos/exynos-pmu.h
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 47b904b..9019d86 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -132,23 +132,6 @@ extern struct smp_operations exynos_smp_ops;
extern void exynos_cpu_die(unsigned int cpu);
-/* PMU(Power Management Unit) support */
-
-#define PMU_TABLE_END (-1U)
-
-enum sys_powerdown {
- SYS_AFTR,
- SYS_LPA,
- SYS_SLEEP,
- NUM_SYS_POWERDOWN,
-};
-
-struct exynos_pmu_conf {
- unsigned int offset;
- unsigned int val[NUM_SYS_POWERDOWN];
-};
-
-extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
extern void exynos_cpu_power_down(int cpu);
extern void exynos_cpu_power_up(int cpu);
extern int exynos_cpu_power_state(int cpu);
diff --git a/arch/arm/mach-exynos/exynos-pmu.h b/arch/arm/mach-exynos/exynos-pmu.h
new file mode 100644
index 0000000..a2ab0d5
--- /dev/null
+++ b/arch/arm/mach-exynos/exynos-pmu.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Header for EXYNOS PMU Driver support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __EXYNOS_PMU_H
+#define __EXYNOS_PMU_H
+
+enum sys_powerdown {
+ SYS_AFTR,
+ SYS_LPA,
+ SYS_SLEEP,
+ NUM_SYS_POWERDOWN,
+};
+
+extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+
+#endif /* __EXYNOS_PMU_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index bcb96be..b2efe8c 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -34,6 +34,7 @@
#include <mach/map.h>
#include "common.h"
+#include "exynos-pmu.h"
#include "regs-pmu.h"
#include "regs-sys.h"
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 5b76728..117f333 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -15,9 +15,16 @@
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
-#include "common.h"
+#include "exynos-pmu.h"
#include "regs-pmu.h"
+#define PMU_TABLE_END (-1U)
+
+struct exynos_pmu_conf {
+ unsigned int offset;
+ unsigned int val[NUM_SYS_POWERDOWN];
+};
+
struct exynos_pmu_data {
const struct exynos_pmu_conf *pmu_config;
const struct exynos_pmu_conf *pmu_config_extra;
@@ -31,8 +38,19 @@ struct exynos_pmu_context {
const struct exynos_pmu_data *pmu_data;
};
+static void __iomem *pmu_base_addr;
static struct exynos_pmu_context *pmu_context;
+static inline void pmu_raw_writel(u32 val, u32 offset)
+{
+ __raw_writel(val, pmu_base_addr + offset);
+}
+
+static inline u32 pmu_raw_readl(u32 offset)
+{
+ return __raw_readl(pmu_base_addr + offset);
+}
+
static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
--
1.7.9.5
^ permalink raw reply related [flat|nested] 35+ messages in thread
* RE: [PATCH v7 1/4] ARM: EXYNOS: Add support for mapping PMU base address via DT
2014-07-09 4:00 ` Pankaj Dubey
@ 2014-07-10 13:49 ` Kukjin Kim
-1 siblings, 0 replies; 35+ messages in thread
From: Kukjin Kim @ 2014-07-10 13:49 UTC (permalink / raw)
To: 'Pankaj Dubey',
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: linux, t.figa, vikas.sajjan, joshi, naushad, thomas.ab, chow.kim
Pankaj Dubey wrote:
>
> Add support for mapping Samsung Power Management Unit (PMU)
> base address from device tree.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> ---
> arch/arm/mach-exynos/common.h | 1 +
> arch/arm/mach-exynos/exynos.c | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index 152b464..f8daa9c 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
>
> extern void __iomem *sysram_ns_base_addr;
> extern void __iomem *sysram_base_addr;
> +extern void __iomem *pmu_base_addr;
> void exynos_sysram_init(void);
>
> void exynos_firmware_init(void);
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index 186f35d..173aac8 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -19,6 +19,7 @@
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/pm_domain.h>
> +#include <linux/irqchip.h>
>
> #include <asm/cacheflush.h>
> #include <asm/hardware/cache-l2x0.h>
> @@ -31,6 +32,8 @@
> #include "regs-pmu.h"
> #include "regs-sys.h"
>
> +void __iomem *pmu_base_addr;
> +
> static struct map_desc exynos4_iodesc[] __initdata = {
> {
> .virtual = (unsigned long)S3C_VA_SYS,
> @@ -253,6 +256,39 @@ static void __init exynos_init_io(void)
> exynos_map_io();
> }
>
> +static const struct of_device_id exynos_dt_pmu_match[] = {
> + { .compatible = "samsung,exynos3250-pmu" },
> + { .compatible = "samsung,exynos4210-pmu" },
> + { .compatible = "samsung,exynos4212-pmu" },
> + { .compatible = "samsung,exynos4412-pmu" },
> + { .compatible = "samsung,exynos5250-pmu" },
> + { .compatible = "samsung,exynos5420-pmu" },
> + { /*sentinel*/ },
> +};
> +
> +static void exynos_map_pmu(void)
> +{
> + struct device_node *np;
> +
> + np = of_find_matching_node(NULL, exynos_dt_pmu_match);
> + if (np)
> + pmu_base_addr = of_iomap(np, 0);
> +
> + if (!pmu_base_addr)
> + panic("failed to find exynos pmu register\n");
> +}
> +
> +static void __init exynos_init_irq(void)
> +{
> + irqchip_init();
> + /*
> + * Since platsmp.c needs pmu base address by the time
> + * DT is not unflatten so we can't use DT APIs before
> + * init_irq
> + */
> + exynos_map_pmu();
> +}
> +
> static void __init exynos_dt_machine_init(void)
> {
> struct device_node *i2c_np;
> @@ -336,6 +372,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
> .smp = smp_ops(exynos_smp_ops),
> .map_io = exynos_init_io,
> .init_early = exynos_firmware_init,
> + .init_irq = exynos_init_irq,
> .init_machine = exynos_dt_machine_init,
> .init_late = exynos_init_late,
> .dt_compat = exynos_dt_compat,
> --
> 1.7.9.5
Looks good to me, will apply.
Thanks,
Kukjin
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 1/4] ARM: EXYNOS: Add support for mapping PMU base address via DT
@ 2014-07-10 13:49 ` Kukjin Kim
0 siblings, 0 replies; 35+ messages in thread
From: Kukjin Kim @ 2014-07-10 13:49 UTC (permalink / raw)
To: linux-arm-kernel
Pankaj Dubey wrote:
>
> Add support for mapping Samsung Power Management Unit (PMU)
> base address from device tree.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> ---
> arch/arm/mach-exynos/common.h | 1 +
> arch/arm/mach-exynos/exynos.c | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index 152b464..f8daa9c 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
>
> extern void __iomem *sysram_ns_base_addr;
> extern void __iomem *sysram_base_addr;
> +extern void __iomem *pmu_base_addr;
> void exynos_sysram_init(void);
>
> void exynos_firmware_init(void);
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index 186f35d..173aac8 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -19,6 +19,7 @@
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/pm_domain.h>
> +#include <linux/irqchip.h>
>
> #include <asm/cacheflush.h>
> #include <asm/hardware/cache-l2x0.h>
> @@ -31,6 +32,8 @@
> #include "regs-pmu.h"
> #include "regs-sys.h"
>
> +void __iomem *pmu_base_addr;
> +
> static struct map_desc exynos4_iodesc[] __initdata = {
> {
> .virtual = (unsigned long)S3C_VA_SYS,
> @@ -253,6 +256,39 @@ static void __init exynos_init_io(void)
> exynos_map_io();
> }
>
> +static const struct of_device_id exynos_dt_pmu_match[] = {
> + { .compatible = "samsung,exynos3250-pmu" },
> + { .compatible = "samsung,exynos4210-pmu" },
> + { .compatible = "samsung,exynos4212-pmu" },
> + { .compatible = "samsung,exynos4412-pmu" },
> + { .compatible = "samsung,exynos5250-pmu" },
> + { .compatible = "samsung,exynos5420-pmu" },
> + { /*sentinel*/ },
> +};
> +
> +static void exynos_map_pmu(void)
> +{
> + struct device_node *np;
> +
> + np = of_find_matching_node(NULL, exynos_dt_pmu_match);
> + if (np)
> + pmu_base_addr = of_iomap(np, 0);
> +
> + if (!pmu_base_addr)
> + panic("failed to find exynos pmu register\n");
> +}
> +
> +static void __init exynos_init_irq(void)
> +{
> + irqchip_init();
> + /*
> + * Since platsmp.c needs pmu base address by the time
> + * DT is not unflatten so we can't use DT APIs before
> + * init_irq
> + */
> + exynos_map_pmu();
> +}
> +
> static void __init exynos_dt_machine_init(void)
> {
> struct device_node *i2c_np;
> @@ -336,6 +372,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
> .smp = smp_ops(exynos_smp_ops),
> .map_io = exynos_init_io,
> .init_early = exynos_firmware_init,
> + .init_irq = exynos_init_irq,
> .init_machine = exynos_dt_machine_init,
> .init_late = exynos_init_late,
> .dt_compat = exynos_dt_compat,
> --
> 1.7.9.5
Looks good to me, will apply.
Thanks,
Kukjin
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v7 2/4] ARM: EXYNOS: Refactored code for using PMU address via DT
2014-07-09 4:00 ` Pankaj Dubey
@ 2014-07-10 13:52 ` Kukjin Kim
-1 siblings, 0 replies; 35+ messages in thread
From: Kukjin Kim @ 2014-07-10 13:52 UTC (permalink / raw)
To: 'Pankaj Dubey',
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: linux, t.figa, vikas.sajjan, joshi, naushad, thomas.ab, chow.kim
Pankaj Dubey wrote:
>
> Under "arm/mach-exynos" many files are using PMU register offsets.
> Since we have added support for accessing PMU base address via DT,
> now we can remove PMU mapping from exynosX_iodesc. Let's convert
> all these access using iomapped address.
> This will help us in removing static mapping of PMU base address
> as well as help in reducing dependency over machine header files.
> Thus helping for migration of PMU implementation from machine to
> driver folder which can be reused for ARM64 bsed SoC.
>
* based
BTW I'm not sure how many stuff from pmu can be reused in ARMv8 exynos SoCs...
> Also as we have removed static mappings from "regs-pmu.h" it does
> not need map.h anymore. But "platsmp.c" needed this and till now it
> got included indirectly. So lets move header inclusion of
> "mach/map.h" from "regs-pmu.h" to "platsmp.c".
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Basic approach looks nice to me, will apply :-)
Thanks,
Kukjin
> ---
> arch/arm/mach-exynos/common.h | 14 +-
> arch/arm/mach-exynos/exynos.c | 12 +-
> arch/arm/mach-exynos/include/mach/map.h | 3 -
> arch/arm/mach-exynos/mcpm-exynos.c | 8 +-
> arch/arm/mach-exynos/platsmp.c | 4 +-
> arch/arm/mach-exynos/pm.c | 76 ++--
> arch/arm/mach-exynos/pmu.c | 40 +-
> arch/arm/mach-exynos/regs-pmu.h | 522 +++++++++++++-------------
> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 -
> 9 files changed, 339 insertions(+), 341 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index f8daa9c..47b904b 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -134,7 +134,7 @@ extern void exynos_cpu_die(unsigned int cpu);
>
> /* PMU(Power Management Unit) support */
>
> -#define PMU_TABLE_END NULL
> +#define PMU_TABLE_END (-1U)
>
> enum sys_powerdown {
> SYS_AFTR,
> @@ -144,7 +144,7 @@ enum sys_powerdown {
> };
>
> struct exynos_pmu_conf {
> - void __iomem *reg;
> + unsigned int offset;
> unsigned int val[NUM_SYS_POWERDOWN];
> };
>
> @@ -160,4 +160,14 @@ extern void exynos_enter_aftr(void);
> extern void s5p_init_cpu(void __iomem *cpuid_addr);
> extern unsigned int samsung_rev(void);
>
> +static inline void pmu_raw_writel(u32 val, u32 offset)
> +{
> + __raw_writel(val, pmu_base_addr + offset);
> +}
> +
> +static inline u32 pmu_raw_readl(u32 offset)
> +{
> + return __raw_readl(pmu_base_addr + offset);
> +}
> +
> #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index 173aac8..d75d3e8 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -61,11 +61,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
> .length = SZ_4K,
> .type = MT_DEVICE,
> }, {
> - .virtual = (unsigned long)S5P_VA_PMU,
> - .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
> - .length = SZ_64K,
> - .type = MT_DEVICE,
> - }, {
> .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
> .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
> .length = SZ_4K,
> @@ -139,11 +134,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
> .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
> .length = 144 * SZ_1K,
> .type = MT_DEVICE,
> - }, {
> - .virtual = (unsigned long)S5P_VA_PMU,
> - .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
> - .length = SZ_64K,
> - .type = MT_DEVICE,
> },
> };
>
> @@ -151,7 +141,7 @@ static void exynos_restart(enum reboot_mode mode, const char *cmd)
> {
> struct device_node *np;
> u32 val = 0x1;
> - void __iomem *addr = EXYNOS_SWRESET;
> + void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
>
> if (of_machine_is_compatible("samsung,exynos5440")) {
> u32 status;
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 963002f..f0b7e92 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -27,9 +27,6 @@
> #define EXYNOS4_PA_SYSCON 0x10010000
> #define EXYNOS5_PA_SYSCON 0x10050100
>
> -#define EXYNOS4_PA_PMU 0x10020000
> -#define EXYNOS5_PA_PMU 0x10040000
> -
> #define EXYNOS4_PA_CMU 0x10030000
> #define EXYNOS5_PA_CMU 0x10010000
>
> diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
> index 9315ba9..70e8ccd 100644
> --- a/arch/arm/mach-exynos/mcpm-exynos.c
> +++ b/arch/arm/mach-exynos/mcpm-exynos.c
> @@ -55,7 +55,7 @@
> "dsb\n\t" \
> "ldmfd sp!, {fp, ip}" \
> : \
> - : "Ir" (S5P_INFORM0) \
> + : "Ir" (pmu_base_addr + S5P_INFORM0) \
> : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
> "r9", "r10", "lr", "memory")
>
> @@ -337,7 +337,7 @@ static int __init exynos_mcpm_init(void)
> * To increase the stability of KFC reset we need to program
> * the PMU SPARE3 register
> */
> - __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
> + pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
>
> exynos_mcpm_usage_count_init();
>
> @@ -366,11 +366,11 @@ static int __init exynos_mcpm_init(void)
> * turned on before the first man is powered up.
> */
> for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
> - value = __raw_readl(EXYNOS_COMMON_OPTION(i));
> + value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
> value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
> EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
> EXYNOS5420_USE_L2_COMMON_UP_STATE;
> - __raw_writel(value, EXYNOS_COMMON_OPTION(i));
> + pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
> }
>
> /*
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index cd25a9c..dab0784 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -26,6 +26,8 @@
> #include <asm/smp_scu.h>
> #include <asm/firmware.h>
>
> +#include <mach/map.h>
> +
> #include "common.h"
> #include "regs-pmu.h"
>
> @@ -34,7 +36,7 @@ extern void exynos4_secondary_startup(void);
> static inline void __iomem *cpu_boot_reg_base(void)
> {
> if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
> - return S5P_INFORM5;
> + return pmu_base_addr + S5P_INFORM5;
> return sysram_base_addr;
> }
>
> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
> index f127c0c..bcb96be 100644
> --- a/arch/arm/mach-exynos/pm.c
> +++ b/arch/arm/mach-exynos/pm.c
> @@ -111,7 +111,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
> */
> void exynos_cpu_power_down(int cpu)
> {
> - __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> + pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> }
>
> /**
> @@ -122,8 +122,8 @@ void exynos_cpu_power_down(int cpu)
> */
> void exynos_cpu_power_up(int cpu)
> {
> - __raw_writel(S5P_CORE_LOCAL_PWR_EN,
> - EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> + pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
> + EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> }
>
> /**
> @@ -133,7 +133,7 @@ void exynos_cpu_power_up(int cpu)
> */
> int exynos_cpu_power_state(int cpu)
> {
> - return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
> + return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
> S5P_CORE_LOCAL_PWR_EN);
> }
>
> @@ -143,7 +143,7 @@ int exynos_cpu_power_state(int cpu)
> */
> void exynos_cluster_power_down(int cluster)
> {
> - __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
> + pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
> }
>
> /**
> @@ -152,8 +152,8 @@ void exynos_cluster_power_down(int cluster)
> */
> void exynos_cluster_power_up(int cluster)
> {
> - __raw_writel(S5P_CORE_LOCAL_PWR_EN,
> - EXYNOS_COMMON_CONFIGURATION(cluster));
> + pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
> + EXYNOS_COMMON_CONFIGURATION(cluster));
> }
>
> /**
> @@ -163,16 +163,20 @@ void exynos_cluster_power_up(int cluster)
> */
> int exynos_cluster_power_state(int cluster)
> {
> - return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
> + return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
> S5P_CORE_LOCAL_PWR_EN);
> }
>
> #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
> - S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
> - (sysram_base_addr + 0x24) : S5P_INFORM0))
> + pmu_base_addr + S5P_INFORM7 : \
> + (samsung_rev() == EXYNOS4210_REV_1_0 ? \
> + (sysram_base_addr + 0x24) : \
> + pmu_base_addr + S5P_INFORM0))
> #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
> - S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
> - (sysram_base_addr + 0x20) : S5P_INFORM1))
> + pmu_base_addr + S5P_INFORM6 : \
> + (samsung_rev() == EXYNOS4210_REV_1_0 ? \
> + (sysram_base_addr + 0x20) : \
> + pmu_base_addr + S5P_INFORM1))
>
> #define S5P_CHECK_AFTR 0xFCBA0D10
> #define S5P_CHECK_SLEEP 0x00000BAD
> @@ -180,7 +184,7 @@ int exynos_cluster_power_state(int cluster)
> /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
> static void exynos_set_wakeupmask(long mask)
> {
> - __raw_writel(mask, S5P_WAKEUP_MASK);
> + pmu_raw_writel(mask, S5P_WAKEUP_MASK);
> }
>
> static void exynos_cpu_set_boot_vector(long flags)
> @@ -257,27 +261,27 @@ static void exynos_pm_prepare(void)
> unsigned int tmp;
>
> /* Set wake-up mask registers */
> - __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
> - __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
> + pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
> + pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
>
> s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
>
> if (soc_is_exynos5250()) {
> s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
> /* Disable USE_RETENTION of JPEG_MEM_OPTION */
> - tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
> + tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
> tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
> - __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
> + pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
> }
>
> /* Set value of power down register for sleep mode */
>
> exynos_sys_powerdown_conf(SYS_SLEEP);
> - __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
> + pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
>
> /* ensure at least INFORM0 has the resume address */
>
> - __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
> + pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
> }
>
> static void exynos_pm_central_suspend(void)
> @@ -285,9 +289,9 @@ static void exynos_pm_central_suspend(void)
> unsigned long tmp;
>
> /* Setting Central Sequence Register for power down mode */
> - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> + tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
> - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
> + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
> }
>
> static int exynos_pm_suspend(void)
> @@ -299,7 +303,7 @@ static int exynos_pm_suspend(void)
> /* Setting SEQ_OPTION register */
>
> tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
> - __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
> + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
>
> if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
> exynos_cpu_save_register();
> @@ -317,12 +321,12 @@ static int exynos_pm_central_resume(void)
> * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
> * in this situation.
> */
> - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> + tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
> tmp |= S5P_CENTRAL_LOWPWR_CFG;
> - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
> + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
> /* clear the wakeup state register */
> - __raw_writel(0x0, S5P_WAKEUP_STAT);
> + pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
> /* No need to perform below restore code */
> return -1;
> }
> @@ -340,13 +344,13 @@ static void exynos_pm_resume(void)
>
> /* For release retention */
>
> - __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
>
> if (soc_is_exynos5250())
> s3c_pm_do_restore(exynos5_sys_save,
> @@ -360,7 +364,7 @@ static void exynos_pm_resume(void)
> early_wakeup:
>
> /* Clear SLEEP mode set in INFORM1 */
> - __raw_writel(0x0, S5P_INFORM1);
> + pmu_raw_writel(0x0, S5P_INFORM1);
>
> return;
> }
> @@ -404,7 +408,7 @@ static int exynos_suspend_enter(suspend_state_t state)
> s3c_pm_restore_uarts();
>
> S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
> - __raw_readl(S5P_WAKEUP_STAT));
> + pmu_raw_readl(S5P_WAKEUP_STAT));
>
> s3c_pm_check_restore();
>
> @@ -475,9 +479,9 @@ void __init exynos_pm_init(void)
> gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
>
> /* All wakeup disable */
> - tmp = __raw_readl(S5P_WAKEUP_MASK);
> + tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
> tmp |= ((0xFF << 8) | (0x1F << 1));
> - __raw_writel(tmp, S5P_WAKEUP_MASK);
> + pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
>
> register_syscore_ops(&exynos_pm_syscore_ops);
> suspend_set_ops(&exynos_suspend_ops);
> diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
> index dcfcb44..ff9d23f 100644
> --- a/arch/arm/mach-exynos/pmu.c
> +++ b/arch/arm/mach-exynos/pmu.c
> @@ -18,7 +18,7 @@
> static const struct exynos_pmu_conf *exynos_pmu_config;
>
> static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
> - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
> + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
> { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
> { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
> { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
> @@ -212,7 +212,7 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
> };
>
> static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
> - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
> + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
> { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
> { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
> { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
> @@ -315,7 +315,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
> { PMU_TABLE_END,},
> };
>
> -static void __iomem * const exynos5_list_both_cnt_feed[] = {
> +static unsigned int const exynos5_list_both_cnt_feed[] = {
> EXYNOS5_ARM_CORE0_OPTION,
> EXYNOS5_ARM_CORE1_OPTION,
> EXYNOS5_ARM_COMMON_OPTION,
> @@ -329,7 +329,7 @@ static void __iomem * const exynos5_list_both_cnt_feed[] = {
> EXYNOS5_TOP_PWR_SYSMEM_OPTION,
> };
>
> -static void __iomem * const exynos5_list_diable_wfi_wfe[] = {
> +static unsigned int const exynos5_list_diable_wfi_wfe[] = {
> EXYNOS5_ARM_CORE1_OPTION,
> EXYNOS5_FSYS_ARM_OPTION,
> EXYNOS5_ISP_ARM_OPTION,
> @@ -344,27 +344,27 @@ static void exynos5_init_pmu(void)
> * Enable both SC_FEEDBACK and SC_COUNTER
> */
> for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
> - tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
> + tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
> tmp |= (EXYNOS5_USE_SC_FEEDBACK |
> EXYNOS5_USE_SC_COUNTER);
> - __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
> + pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
> }
>
> /*
> * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
> */
> - tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
> + tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
> tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
> - __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
> + pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
>
> /*
> * Disable WFI/WFE on XXX_OPTION
> */
> for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
> - tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
> + tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
> tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
> EXYNOS5_OPTION_USE_STANDBYWFI);
> - __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
> + pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
> }
> }
>
> @@ -375,14 +375,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
> if (soc_is_exynos5250())
> exynos5_init_pmu();
>
> - for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
> - __raw_writel(exynos_pmu_config[i].val[mode],
> - exynos_pmu_config[i].reg);
> + for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
> + pmu_raw_writel(exynos_pmu_config[i].val[mode],
> + exynos_pmu_config[i].offset);
>
> if (soc_is_exynos4412()) {
> - for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
> - __raw_writel(exynos4412_pmu_config[i].val[mode],
> - exynos4412_pmu_config[i].reg);
> + for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
> + pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
> + exynos4412_pmu_config[i].offset);
> }
> }
>
> @@ -403,13 +403,13 @@ static int __init exynos_pmu_init(void)
> * When SYS_WDTRESET is set, watchdog timer reset request
> * is ignored by power management unit.
> */
> - value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> + value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> value &= ~EXYNOS5_SYS_WDTRESET;
> - __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
> + pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
>
> - value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> + value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> value &= ~EXYNOS5_SYS_WDTRESET;
> - __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
> + pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
>
> exynos_pmu_config = exynos5250_pmu_config;
> pr_info("EXYNOS5250 PMU Initialize\n");
> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
> index e5e298c..96a1569 100644
> --- a/arch/arm/mach-exynos/regs-pmu.h
> +++ b/arch/arm/mach-exynos/regs-pmu.h
> @@ -12,106 +12,102 @@
> #ifndef __ASM_ARCH_REGS_PMU_H
> #define __ASM_ARCH_REGS_PMU_H __FILE__
>
> -#include <mach/map.h>
> -
> -#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
> -
> -#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
> +#define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
>
> #define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
>
> -#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
> +#define S5P_CENTRAL_SEQ_OPTION 0x0208
>
> #define S5P_USE_STANDBY_WFI0 (1 << 16)
> #define S5P_USE_STANDBY_WFE0 (1 << 24)
>
> -#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
> -#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
> -
> -#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
> -#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
> -#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
> -
> -#define S5P_INFORM0 S5P_PMUREG(0x0800)
> -#define S5P_INFORM1 S5P_PMUREG(0x0804)
> -#define S5P_INFORM5 S5P_PMUREG(0x0814)
> -#define S5P_INFORM6 S5P_PMUREG(0x0818)
> -#define S5P_INFORM7 S5P_PMUREG(0x081C)
> -#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C)
> -
> -#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
> -#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
> -#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
> -#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
> -#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
> -#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
> -#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
> -#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
> -#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
> -#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
> -#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
> -#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
> -#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
> -#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
> -#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
> -#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
> -#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
> -#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
> -#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
> -#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
> -#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
> -#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
> -#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
> -#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
> -#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
> -#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
> -#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
> -#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
> -#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
> -#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
> -#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
> -#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
> -#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
> -#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
> -#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
> -#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
> -#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
> -#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
> -#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
> -#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
> -#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
> -#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
> -#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
> -#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
> -#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
> -#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
> -#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
> -#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
> -#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
> -#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
> -#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
> -#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
> -#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
> -#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
> -#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
> -#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
> -#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
> -#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
> -#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
> -#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
> -#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
> -#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
> -#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
> -#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
> -#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
> -
> -#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
> +#define EXYNOS_SWRESET 0x0400
> +#define EXYNOS5440_SWRESET 0x00C4
> +
> +#define S5P_WAKEUP_STAT 0x0600
> +#define S5P_EINT_WAKEUP_MASK 0x0604
> +#define S5P_WAKEUP_MASK 0x0608
> +
> +#define S5P_INFORM0 0x0800
> +#define S5P_INFORM1 0x0804
> +#define S5P_INFORM5 0x0814
> +#define S5P_INFORM6 0x0818
> +#define S5P_INFORM7 0x081C
> +#define S5P_PMU_SPARE3 0x090C
> +
> +#define S5P_ARM_CORE0_LOWPWR 0x1000
> +#define S5P_DIS_IRQ_CORE0 0x1004
> +#define S5P_DIS_IRQ_CENTRAL0 0x1008
> +#define S5P_ARM_CORE1_LOWPWR 0x1010
> +#define S5P_DIS_IRQ_CORE1 0x1014
> +#define S5P_DIS_IRQ_CENTRAL1 0x1018
> +#define S5P_ARM_COMMON_LOWPWR 0x1080
> +#define S5P_L2_0_LOWPWR 0x10C0
> +#define S5P_L2_1_LOWPWR 0x10C4
> +#define S5P_CMU_ACLKSTOP_LOWPWR 0x1100
> +#define S5P_CMU_SCLKSTOP_LOWPWR 0x1104
> +#define S5P_CMU_RESET_LOWPWR 0x110C
> +#define S5P_APLL_SYSCLK_LOWPWR 0x1120
> +#define S5P_MPLL_SYSCLK_LOWPWR 0x1124
> +#define S5P_VPLL_SYSCLK_LOWPWR 0x1128
> +#define S5P_EPLL_SYSCLK_LOWPWR 0x112C
> +#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138
> +#define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C
> +#define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140
> +#define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144
> +#define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148
> +#define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C
> +#define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150
> +#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158
> +#define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C
> +#define S5P_CMU_RESET_CAM_LOWPWR 0x1160
> +#define S5P_CMU_RESET_TV_LOWPWR 0x1164
> +#define S5P_CMU_RESET_MFC_LOWPWR 0x1168
> +#define S5P_CMU_RESET_G3D_LOWPWR 0x116C
> +#define S5P_CMU_RESET_LCD0_LOWPWR 0x1170
> +#define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178
> +#define S5P_CMU_RESET_GPS_LOWPWR 0x117C
> +#define S5P_TOP_BUS_LOWPWR 0x1180
> +#define S5P_TOP_RETENTION_LOWPWR 0x1184
> +#define S5P_TOP_PWR_LOWPWR 0x1188
> +#define S5P_LOGIC_RESET_LOWPWR 0x11A0
> +#define S5P_ONENAND_MEM_LOWPWR 0x11C0
> +#define S5P_G2D_ACP_MEM_LOWPWR 0x11C8
> +#define S5P_USBOTG_MEM_LOWPWR 0x11CC
> +#define S5P_HSMMC_MEM_LOWPWR 0x11D0
> +#define S5P_CSSYS_MEM_LOWPWR 0x11D4
> +#define S5P_SECSS_MEM_LOWPWR 0x11D8
> +#define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200
> +#define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204
> +#define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220
> +#define S5P_PAD_RETENTION_UART_LOWPWR 0x1224
> +#define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228
> +#define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C
> +#define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230
> +#define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234
> +#define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240
> +#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260
> +#define S5P_XUSBXTI_LOWPWR 0x1280
> +#define S5P_XXTI_LOWPWR 0x1284
> +#define S5P_EXT_REGULATOR_LOWPWR 0x12C0
> +#define S5P_GPIO_MODE_LOWPWR 0x1300
> +#define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340
> +#define S5P_CAM_LOWPWR 0x1380
> +#define S5P_TV_LOWPWR 0x1384
> +#define S5P_MFC_LOWPWR 0x1388
> +#define S5P_G3D_LOWPWR 0x138C
> +#define S5P_LCD0_LOWPWR 0x1390
> +#define S5P_MAUDIO_LOWPWR 0x1398
> +#define S5P_GPS_LOWPWR 0x139C
> +#define S5P_GPS_ALIVE_LOWPWR 0x13A0
> +
> +#define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000
> #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
> (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
> #define EXYNOS_ARM_CORE_STATUS(_nr) \
> (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
>
> -#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500)
> +#define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500
> #define EXYNOS_COMMON_CONFIGURATION(_nr) \
> (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
> #define EXYNOS_COMMON_STATUS(_nr) \
> @@ -119,195 +115,195 @@
> #define EXYNOS_COMMON_OPTION(_nr) \
> (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
>
> -#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
> -#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
> -#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
> -#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
> -#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
> -#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
> -#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
> +#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
> +#define S5P_PAD_RET_GPIO_OPTION 0x3108
> +#define S5P_PAD_RET_UART_OPTION 0x3128
> +#define S5P_PAD_RET_MMCA_OPTION 0x3148
> +#define S5P_PAD_RET_MMCB_OPTION 0x3168
> +#define S5P_PAD_RET_EBIA_OPTION 0x3188
> +#define S5P_PAD_RET_EBIB_OPTION 0x31A8
>
> #define S5P_CORE_LOCAL_PWR_EN 0x3
>
> /* Only for EXYNOS4210 */
> -#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
> -#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
> -#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
> -#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
> -#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
> -#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
> +#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
> +#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
> +#define S5P_MODIMIF_MEM_LOWPWR 0x11C4
> +#define S5P_PCIE_MEM_LOWPWR 0x11E0
> +#define S5P_SATA_MEM_LOWPWR 0x11E4
> +#define S5P_LCD1_LOWPWR 0x1394
>
> /* Only for EXYNOS4x12 */
> -#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
> -#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
> -#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
> -#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
> -#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
> -#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
> -#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
> -#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
> -#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
> -#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
> -#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
> -#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
> -#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
> -#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
> -#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
> -#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
> -#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
> -#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
> -#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
> -#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
> -#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
> -#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
> -#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
> -#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
> -#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
> -#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
> -#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
> -#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
> -
> -#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
> -#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
> -#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
> -#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
> -#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
> -#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
> -#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
> -#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
> -#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
> -#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
> +#define S5P_ISP_ARM_LOWPWR 0x1050
> +#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054
> +#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058
> +#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110
> +#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114
> +#define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C
> +#define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130
> +#define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154
> +#define S5P_CMU_RESET_ISP_LOWPWR 0x1174
> +#define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190
> +#define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194
> +#define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198
> +#define S5P_OSCCLK_GATE_LOWPWR 0x11A4
> +#define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0
> +#define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4
> +#define S5P_HSI_MEM_LOWPWR 0x11C4
> +#define S5P_ROTATOR_MEM_LOWPWR 0x11DC
> +#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C
> +#define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250
> +#define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320
> +#define S5P_TOP_ASB_RESET_LOWPWR 0x1344
> +#define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348
> +#define S5P_ISP_LOWPWR 0x1394
> +#define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0
> +#define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4
> +#define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8
> +#define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC
> +#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0
> +
> +#define S5P_ARM_L2_0_OPTION 0x2608
> +#define S5P_ARM_L2_1_OPTION 0x2628
> +#define S5P_ONENAND_MEM_OPTION 0x2E08
> +#define S5P_HSI_MEM_OPTION 0x2E28
> +#define S5P_G2D_ACP_MEM_OPTION 0x2E48
> +#define S5P_USBOTG_MEM_OPTION 0x2E68
> +#define S5P_HSMMC_MEM_OPTION 0x2E88
> +#define S5P_CSSYS_MEM_OPTION 0x2EA8
> +#define S5P_SECSS_MEM_OPTION 0x2EC8
> +#define S5P_ROTATOR_MEM_OPTION 0x2F48
>
> /* Only for EXYNOS4412 */
> -#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
> -#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
> -#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
> -#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
> -#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
> -#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
> +#define S5P_ARM_CORE2_LOWPWR 0x1020
> +#define S5P_DIS_IRQ_CORE2 0x1024
> +#define S5P_DIS_IRQ_CENTRAL2 0x1028
> +#define S5P_ARM_CORE3_LOWPWR 0x1030
> +#define S5P_DIS_IRQ_CORE3 0x1034
> +#define S5P_DIS_IRQ_CENTRAL3 0x1038
>
> /* For EXYNOS5 */
>
> -#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
> -#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
> +#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
> +#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
>
> #define EXYNOS5_SYS_WDTRESET (1 << 20)
>
> -#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
> -#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
> -#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
> -#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
> -#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
> -#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
> -#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
> -#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
> -#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
> -#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
> -#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
> -#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
> -#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
> -#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
> -#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
> -#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
> -#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
> -#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
> -#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
> -#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
> -#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
> -#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
> -#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
> -#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
> -#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
> -#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
> -#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
> -#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
> -#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
> -#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
> -#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
> -#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
> -#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
> -#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
> -#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
> -#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
> -#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
> -#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
> -#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
> -#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
> -#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
> -#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
> -#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
> -#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
> -#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
> -#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
> -#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
> -#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
> -#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
> -#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
> -#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
> -#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
> -#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
> -#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
> -#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
> -#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
> -#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
> -#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
> -#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
> -#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
> -#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
> -#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
> -#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
> -#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
> -#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
> -#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
> -#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
> -#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
> -#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
> -#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
> -#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
> -#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
> -#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
> -#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
> -#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
> -#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
> -#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
> -#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
> -#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
> -#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
> -#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
> -#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
> -#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
> -#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
> -#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
> -#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
> -#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
> -#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
> -#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
> -#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
> -#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
> -#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
> -#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
> -#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
> -#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
> -#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
> -#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
> -#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
> -#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
> -
> -#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
> -#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
> -#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
> -#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
> -#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
> -#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608)
> -#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
> -#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
> -#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
> -#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
> -#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
> -#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
> -#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
> -#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
> -#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
> +#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
> +#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
> +#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
> +#define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010
> +#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
> +#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
> +#define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040
> +#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048
> +#define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050
> +#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
> +#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
> +#define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080
> +#define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0
> +#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
> +#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
> +#define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C
> +#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120
> +#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124
> +#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C
> +#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130
> +#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134
> +#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138
> +#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140
> +#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144
> +#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148
> +#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C
> +#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150
> +#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154
> +#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164
> +#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170
> +#define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180
> +#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184
> +#define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188
> +#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190
> +#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194
> +#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198
> +#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0
> +#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4
> +#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0
> +#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4
> +#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0
> +#define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8
> +#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC
> +#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0
> +#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4
> +#define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8
> +#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC
> +#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0
> +#define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4
> +#define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8
> +#define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC
> +#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4
> +#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
> +#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
> +#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
> +#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208
> +#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
> +#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
> +#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
> +#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
> +#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
> +#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
> +#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238
> +#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C
> +#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240
> +#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250
> +#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260
> +#define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280
> +#define EXYNOS5_XXTI_SYS_PWR_REG 0x1284
> +#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0
> +#define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300
> +#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320
> +#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340
> +#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344
> +#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
> +#define EXYNOS5_GSCL_SYS_PWR_REG 0x1400
> +#define EXYNOS5_ISP_SYS_PWR_REG 0x1404
> +#define EXYNOS5_MFC_SYS_PWR_REG 0x1408
> +#define EXYNOS5_G3D_SYS_PWR_REG 0x140C
> +#define EXYNOS5_DISP1_SYS_PWR_REG 0x1414
> +#define EXYNOS5_MAU_SYS_PWR_REG 0x1418
> +#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480
> +#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484
> +#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488
> +#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C
> +#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494
> +#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498
> +#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0
> +#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4
> +#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8
> +#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC
> +#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4
> +#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8
> +#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580
> +#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584
> +#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588
> +#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C
> +#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594
> +#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598
> +
> +#define EXYNOS5_ARM_CORE0_OPTION 0x2008
> +#define EXYNOS5_ARM_CORE1_OPTION 0x2088
> +#define EXYNOS5_FSYS_ARM_OPTION 0x2208
> +#define EXYNOS5_ISP_ARM_OPTION 0x2288
> +#define EXYNOS5_ARM_COMMON_OPTION 0x2408
> +#define EXYNOS5_ARM_L2_OPTION 0x2608
> +#define EXYNOS5_TOP_PWR_OPTION 0x2C48
> +#define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8
> +#define EXYNOS5_JPEG_MEM_OPTION 0x2F48
> +#define EXYNOS5_GSCL_OPTION 0x4008
> +#define EXYNOS5_ISP_OPTION 0x4028
> +#define EXYNOS5_MFC_OPTION 0x4048
> +#define EXYNOS5_G3D_OPTION 0x4068
> +#define EXYNOS5_DISP1_OPTION 0x40A8
> +#define EXYNOS5_MAU_OPTION 0x40C8
>
> #define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
> #define EXYNOS5_USE_SC_COUNTER (1 << 0)
> diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-
> s5p.h
> index c186786..f5b9d3f 100644
> --- a/arch/arm/plat-samsung/include/plat/map-s5p.h
> +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
> @@ -15,7 +15,6 @@
>
> #define S5P_VA_CHIPID S3C_ADDR(0x02000000)
> #define S5P_VA_CMU S3C_ADDR(0x02100000)
> -#define S5P_VA_PMU S3C_ADDR(0x02180000)
> #define S5P_VA_GPIO S3C_ADDR(0x02200000)
> #define S5P_VA_GPIO1 S5P_VA_GPIO
> #define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
> --
> 1.7.9.5
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 2/4] ARM: EXYNOS: Refactored code for using PMU address via DT
@ 2014-07-10 13:52 ` Kukjin Kim
0 siblings, 0 replies; 35+ messages in thread
From: Kukjin Kim @ 2014-07-10 13:52 UTC (permalink / raw)
To: linux-arm-kernel
Pankaj Dubey wrote:
>
> Under "arm/mach-exynos" many files are using PMU register offsets.
> Since we have added support for accessing PMU base address via DT,
> now we can remove PMU mapping from exynosX_iodesc. Let's convert
> all these access using iomapped address.
> This will help us in removing static mapping of PMU base address
> as well as help in reducing dependency over machine header files.
> Thus helping for migration of PMU implementation from machine to
> driver folder which can be reused for ARM64 bsed SoC.
>
* based
BTW I'm not sure how many stuff from pmu can be reused in ARMv8 exynos SoCs...
> Also as we have removed static mappings from "regs-pmu.h" it does
> not need map.h anymore. But "platsmp.c" needed this and till now it
> got included indirectly. So lets move header inclusion of
> "mach/map.h" from "regs-pmu.h" to "platsmp.c".
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Basic approach looks nice to me, will apply :-)
Thanks,
Kukjin
> ---
> arch/arm/mach-exynos/common.h | 14 +-
> arch/arm/mach-exynos/exynos.c | 12 +-
> arch/arm/mach-exynos/include/mach/map.h | 3 -
> arch/arm/mach-exynos/mcpm-exynos.c | 8 +-
> arch/arm/mach-exynos/platsmp.c | 4 +-
> arch/arm/mach-exynos/pm.c | 76 ++--
> arch/arm/mach-exynos/pmu.c | 40 +-
> arch/arm/mach-exynos/regs-pmu.h | 522 +++++++++++++-------------
> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 -
> 9 files changed, 339 insertions(+), 341 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index f8daa9c..47b904b 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -134,7 +134,7 @@ extern void exynos_cpu_die(unsigned int cpu);
>
> /* PMU(Power Management Unit) support */
>
> -#define PMU_TABLE_END NULL
> +#define PMU_TABLE_END (-1U)
>
> enum sys_powerdown {
> SYS_AFTR,
> @@ -144,7 +144,7 @@ enum sys_powerdown {
> };
>
> struct exynos_pmu_conf {
> - void __iomem *reg;
> + unsigned int offset;
> unsigned int val[NUM_SYS_POWERDOWN];
> };
>
> @@ -160,4 +160,14 @@ extern void exynos_enter_aftr(void);
> extern void s5p_init_cpu(void __iomem *cpuid_addr);
> extern unsigned int samsung_rev(void);
>
> +static inline void pmu_raw_writel(u32 val, u32 offset)
> +{
> + __raw_writel(val, pmu_base_addr + offset);
> +}
> +
> +static inline u32 pmu_raw_readl(u32 offset)
> +{
> + return __raw_readl(pmu_base_addr + offset);
> +}
> +
> #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index 173aac8..d75d3e8 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -61,11 +61,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
> .length = SZ_4K,
> .type = MT_DEVICE,
> }, {
> - .virtual = (unsigned long)S5P_VA_PMU,
> - .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
> - .length = SZ_64K,
> - .type = MT_DEVICE,
> - }, {
> .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
> .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
> .length = SZ_4K,
> @@ -139,11 +134,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
> .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
> .length = 144 * SZ_1K,
> .type = MT_DEVICE,
> - }, {
> - .virtual = (unsigned long)S5P_VA_PMU,
> - .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
> - .length = SZ_64K,
> - .type = MT_DEVICE,
> },
> };
>
> @@ -151,7 +141,7 @@ static void exynos_restart(enum reboot_mode mode, const char *cmd)
> {
> struct device_node *np;
> u32 val = 0x1;
> - void __iomem *addr = EXYNOS_SWRESET;
> + void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
>
> if (of_machine_is_compatible("samsung,exynos5440")) {
> u32 status;
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 963002f..f0b7e92 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -27,9 +27,6 @@
> #define EXYNOS4_PA_SYSCON 0x10010000
> #define EXYNOS5_PA_SYSCON 0x10050100
>
> -#define EXYNOS4_PA_PMU 0x10020000
> -#define EXYNOS5_PA_PMU 0x10040000
> -
> #define EXYNOS4_PA_CMU 0x10030000
> #define EXYNOS5_PA_CMU 0x10010000
>
> diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
> index 9315ba9..70e8ccd 100644
> --- a/arch/arm/mach-exynos/mcpm-exynos.c
> +++ b/arch/arm/mach-exynos/mcpm-exynos.c
> @@ -55,7 +55,7 @@
> "dsb\n\t" \
> "ldmfd sp!, {fp, ip}" \
> : \
> - : "Ir" (S5P_INFORM0) \
> + : "Ir" (pmu_base_addr + S5P_INFORM0) \
> : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
> "r9", "r10", "lr", "memory")
>
> @@ -337,7 +337,7 @@ static int __init exynos_mcpm_init(void)
> * To increase the stability of KFC reset we need to program
> * the PMU SPARE3 register
> */
> - __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
> + pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
>
> exynos_mcpm_usage_count_init();
>
> @@ -366,11 +366,11 @@ static int __init exynos_mcpm_init(void)
> * turned on before the first man is powered up.
> */
> for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
> - value = __raw_readl(EXYNOS_COMMON_OPTION(i));
> + value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
> value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
> EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
> EXYNOS5420_USE_L2_COMMON_UP_STATE;
> - __raw_writel(value, EXYNOS_COMMON_OPTION(i));
> + pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
> }
>
> /*
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index cd25a9c..dab0784 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -26,6 +26,8 @@
> #include <asm/smp_scu.h>
> #include <asm/firmware.h>
>
> +#include <mach/map.h>
> +
> #include "common.h"
> #include "regs-pmu.h"
>
> @@ -34,7 +36,7 @@ extern void exynos4_secondary_startup(void);
> static inline void __iomem *cpu_boot_reg_base(void)
> {
> if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
> - return S5P_INFORM5;
> + return pmu_base_addr + S5P_INFORM5;
> return sysram_base_addr;
> }
>
> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
> index f127c0c..bcb96be 100644
> --- a/arch/arm/mach-exynos/pm.c
> +++ b/arch/arm/mach-exynos/pm.c
> @@ -111,7 +111,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
> */
> void exynos_cpu_power_down(int cpu)
> {
> - __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> + pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> }
>
> /**
> @@ -122,8 +122,8 @@ void exynos_cpu_power_down(int cpu)
> */
> void exynos_cpu_power_up(int cpu)
> {
> - __raw_writel(S5P_CORE_LOCAL_PWR_EN,
> - EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> + pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
> + EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> }
>
> /**
> @@ -133,7 +133,7 @@ void exynos_cpu_power_up(int cpu)
> */
> int exynos_cpu_power_state(int cpu)
> {
> - return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
> + return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
> S5P_CORE_LOCAL_PWR_EN);
> }
>
> @@ -143,7 +143,7 @@ int exynos_cpu_power_state(int cpu)
> */
> void exynos_cluster_power_down(int cluster)
> {
> - __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
> + pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
> }
>
> /**
> @@ -152,8 +152,8 @@ void exynos_cluster_power_down(int cluster)
> */
> void exynos_cluster_power_up(int cluster)
> {
> - __raw_writel(S5P_CORE_LOCAL_PWR_EN,
> - EXYNOS_COMMON_CONFIGURATION(cluster));
> + pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
> + EXYNOS_COMMON_CONFIGURATION(cluster));
> }
>
> /**
> @@ -163,16 +163,20 @@ void exynos_cluster_power_up(int cluster)
> */
> int exynos_cluster_power_state(int cluster)
> {
> - return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
> + return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
> S5P_CORE_LOCAL_PWR_EN);
> }
>
> #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
> - S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
> - (sysram_base_addr + 0x24) : S5P_INFORM0))
> + pmu_base_addr + S5P_INFORM7 : \
> + (samsung_rev() == EXYNOS4210_REV_1_0 ? \
> + (sysram_base_addr + 0x24) : \
> + pmu_base_addr + S5P_INFORM0))
> #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
> - S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
> - (sysram_base_addr + 0x20) : S5P_INFORM1))
> + pmu_base_addr + S5P_INFORM6 : \
> + (samsung_rev() == EXYNOS4210_REV_1_0 ? \
> + (sysram_base_addr + 0x20) : \
> + pmu_base_addr + S5P_INFORM1))
>
> #define S5P_CHECK_AFTR 0xFCBA0D10
> #define S5P_CHECK_SLEEP 0x00000BAD
> @@ -180,7 +184,7 @@ int exynos_cluster_power_state(int cluster)
> /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
> static void exynos_set_wakeupmask(long mask)
> {
> - __raw_writel(mask, S5P_WAKEUP_MASK);
> + pmu_raw_writel(mask, S5P_WAKEUP_MASK);
> }
>
> static void exynos_cpu_set_boot_vector(long flags)
> @@ -257,27 +261,27 @@ static void exynos_pm_prepare(void)
> unsigned int tmp;
>
> /* Set wake-up mask registers */
> - __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
> - __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
> + pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
> + pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
>
> s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
>
> if (soc_is_exynos5250()) {
> s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
> /* Disable USE_RETENTION of JPEG_MEM_OPTION */
> - tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
> + tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
> tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
> - __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
> + pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
> }
>
> /* Set value of power down register for sleep mode */
>
> exynos_sys_powerdown_conf(SYS_SLEEP);
> - __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
> + pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
>
> /* ensure at least INFORM0 has the resume address */
>
> - __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
> + pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
> }
>
> static void exynos_pm_central_suspend(void)
> @@ -285,9 +289,9 @@ static void exynos_pm_central_suspend(void)
> unsigned long tmp;
>
> /* Setting Central Sequence Register for power down mode */
> - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> + tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
> - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
> + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
> }
>
> static int exynos_pm_suspend(void)
> @@ -299,7 +303,7 @@ static int exynos_pm_suspend(void)
> /* Setting SEQ_OPTION register */
>
> tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
> - __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
> + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
>
> if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
> exynos_cpu_save_register();
> @@ -317,12 +321,12 @@ static int exynos_pm_central_resume(void)
> * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
> * in this situation.
> */
> - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> + tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
> tmp |= S5P_CENTRAL_LOWPWR_CFG;
> - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
> + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
> /* clear the wakeup state register */
> - __raw_writel(0x0, S5P_WAKEUP_STAT);
> + pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
> /* No need to perform below restore code */
> return -1;
> }
> @@ -340,13 +344,13 @@ static void exynos_pm_resume(void)
>
> /* For release retention */
>
> - __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
> - __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
> + pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
>
> if (soc_is_exynos5250())
> s3c_pm_do_restore(exynos5_sys_save,
> @@ -360,7 +364,7 @@ static void exynos_pm_resume(void)
> early_wakeup:
>
> /* Clear SLEEP mode set in INFORM1 */
> - __raw_writel(0x0, S5P_INFORM1);
> + pmu_raw_writel(0x0, S5P_INFORM1);
>
> return;
> }
> @@ -404,7 +408,7 @@ static int exynos_suspend_enter(suspend_state_t state)
> s3c_pm_restore_uarts();
>
> S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
> - __raw_readl(S5P_WAKEUP_STAT));
> + pmu_raw_readl(S5P_WAKEUP_STAT));
>
> s3c_pm_check_restore();
>
> @@ -475,9 +479,9 @@ void __init exynos_pm_init(void)
> gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
>
> /* All wakeup disable */
> - tmp = __raw_readl(S5P_WAKEUP_MASK);
> + tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
> tmp |= ((0xFF << 8) | (0x1F << 1));
> - __raw_writel(tmp, S5P_WAKEUP_MASK);
> + pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
>
> register_syscore_ops(&exynos_pm_syscore_ops);
> suspend_set_ops(&exynos_suspend_ops);
> diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
> index dcfcb44..ff9d23f 100644
> --- a/arch/arm/mach-exynos/pmu.c
> +++ b/arch/arm/mach-exynos/pmu.c
> @@ -18,7 +18,7 @@
> static const struct exynos_pmu_conf *exynos_pmu_config;
>
> static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
> - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
> + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
> { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
> { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
> { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
> @@ -212,7 +212,7 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
> };
>
> static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
> - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
> + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
> { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
> { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
> { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
> @@ -315,7 +315,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
> { PMU_TABLE_END,},
> };
>
> -static void __iomem * const exynos5_list_both_cnt_feed[] = {
> +static unsigned int const exynos5_list_both_cnt_feed[] = {
> EXYNOS5_ARM_CORE0_OPTION,
> EXYNOS5_ARM_CORE1_OPTION,
> EXYNOS5_ARM_COMMON_OPTION,
> @@ -329,7 +329,7 @@ static void __iomem * const exynos5_list_both_cnt_feed[] = {
> EXYNOS5_TOP_PWR_SYSMEM_OPTION,
> };
>
> -static void __iomem * const exynos5_list_diable_wfi_wfe[] = {
> +static unsigned int const exynos5_list_diable_wfi_wfe[] = {
> EXYNOS5_ARM_CORE1_OPTION,
> EXYNOS5_FSYS_ARM_OPTION,
> EXYNOS5_ISP_ARM_OPTION,
> @@ -344,27 +344,27 @@ static void exynos5_init_pmu(void)
> * Enable both SC_FEEDBACK and SC_COUNTER
> */
> for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
> - tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
> + tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
> tmp |= (EXYNOS5_USE_SC_FEEDBACK |
> EXYNOS5_USE_SC_COUNTER);
> - __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
> + pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
> }
>
> /*
> * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
> */
> - tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
> + tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
> tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
> - __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
> + pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
>
> /*
> * Disable WFI/WFE on XXX_OPTION
> */
> for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
> - tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
> + tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
> tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
> EXYNOS5_OPTION_USE_STANDBYWFI);
> - __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
> + pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
> }
> }
>
> @@ -375,14 +375,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
> if (soc_is_exynos5250())
> exynos5_init_pmu();
>
> - for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
> - __raw_writel(exynos_pmu_config[i].val[mode],
> - exynos_pmu_config[i].reg);
> + for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
> + pmu_raw_writel(exynos_pmu_config[i].val[mode],
> + exynos_pmu_config[i].offset);
>
> if (soc_is_exynos4412()) {
> - for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
> - __raw_writel(exynos4412_pmu_config[i].val[mode],
> - exynos4412_pmu_config[i].reg);
> + for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
> + pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
> + exynos4412_pmu_config[i].offset);
> }
> }
>
> @@ -403,13 +403,13 @@ static int __init exynos_pmu_init(void)
> * When SYS_WDTRESET is set, watchdog timer reset request
> * is ignored by power management unit.
> */
> - value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> + value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> value &= ~EXYNOS5_SYS_WDTRESET;
> - __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
> + pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
>
> - value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> + value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> value &= ~EXYNOS5_SYS_WDTRESET;
> - __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
> + pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
>
> exynos_pmu_config = exynos5250_pmu_config;
> pr_info("EXYNOS5250 PMU Initialize\n");
> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
> index e5e298c..96a1569 100644
> --- a/arch/arm/mach-exynos/regs-pmu.h
> +++ b/arch/arm/mach-exynos/regs-pmu.h
> @@ -12,106 +12,102 @@
> #ifndef __ASM_ARCH_REGS_PMU_H
> #define __ASM_ARCH_REGS_PMU_H __FILE__
>
> -#include <mach/map.h>
> -
> -#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
> -
> -#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
> +#define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
>
> #define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
>
> -#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
> +#define S5P_CENTRAL_SEQ_OPTION 0x0208
>
> #define S5P_USE_STANDBY_WFI0 (1 << 16)
> #define S5P_USE_STANDBY_WFE0 (1 << 24)
>
> -#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
> -#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
> -
> -#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
> -#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
> -#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
> -
> -#define S5P_INFORM0 S5P_PMUREG(0x0800)
> -#define S5P_INFORM1 S5P_PMUREG(0x0804)
> -#define S5P_INFORM5 S5P_PMUREG(0x0814)
> -#define S5P_INFORM6 S5P_PMUREG(0x0818)
> -#define S5P_INFORM7 S5P_PMUREG(0x081C)
> -#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C)
> -
> -#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
> -#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
> -#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
> -#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
> -#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
> -#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
> -#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
> -#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
> -#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
> -#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
> -#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
> -#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
> -#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
> -#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
> -#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
> -#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
> -#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
> -#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
> -#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
> -#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
> -#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
> -#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
> -#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
> -#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
> -#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
> -#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
> -#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
> -#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
> -#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
> -#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
> -#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
> -#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
> -#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
> -#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
> -#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
> -#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
> -#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
> -#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
> -#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
> -#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
> -#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
> -#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
> -#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
> -#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
> -#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
> -#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
> -#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
> -#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
> -#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
> -#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
> -#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
> -#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
> -#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
> -#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
> -#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
> -#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
> -#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
> -#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
> -#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
> -#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
> -#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
> -#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
> -#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
> -#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
> -#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
> -
> -#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
> +#define EXYNOS_SWRESET 0x0400
> +#define EXYNOS5440_SWRESET 0x00C4
> +
> +#define S5P_WAKEUP_STAT 0x0600
> +#define S5P_EINT_WAKEUP_MASK 0x0604
> +#define S5P_WAKEUP_MASK 0x0608
> +
> +#define S5P_INFORM0 0x0800
> +#define S5P_INFORM1 0x0804
> +#define S5P_INFORM5 0x0814
> +#define S5P_INFORM6 0x0818
> +#define S5P_INFORM7 0x081C
> +#define S5P_PMU_SPARE3 0x090C
> +
> +#define S5P_ARM_CORE0_LOWPWR 0x1000
> +#define S5P_DIS_IRQ_CORE0 0x1004
> +#define S5P_DIS_IRQ_CENTRAL0 0x1008
> +#define S5P_ARM_CORE1_LOWPWR 0x1010
> +#define S5P_DIS_IRQ_CORE1 0x1014
> +#define S5P_DIS_IRQ_CENTRAL1 0x1018
> +#define S5P_ARM_COMMON_LOWPWR 0x1080
> +#define S5P_L2_0_LOWPWR 0x10C0
> +#define S5P_L2_1_LOWPWR 0x10C4
> +#define S5P_CMU_ACLKSTOP_LOWPWR 0x1100
> +#define S5P_CMU_SCLKSTOP_LOWPWR 0x1104
> +#define S5P_CMU_RESET_LOWPWR 0x110C
> +#define S5P_APLL_SYSCLK_LOWPWR 0x1120
> +#define S5P_MPLL_SYSCLK_LOWPWR 0x1124
> +#define S5P_VPLL_SYSCLK_LOWPWR 0x1128
> +#define S5P_EPLL_SYSCLK_LOWPWR 0x112C
> +#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138
> +#define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C
> +#define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140
> +#define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144
> +#define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148
> +#define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C
> +#define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150
> +#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158
> +#define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C
> +#define S5P_CMU_RESET_CAM_LOWPWR 0x1160
> +#define S5P_CMU_RESET_TV_LOWPWR 0x1164
> +#define S5P_CMU_RESET_MFC_LOWPWR 0x1168
> +#define S5P_CMU_RESET_G3D_LOWPWR 0x116C
> +#define S5P_CMU_RESET_LCD0_LOWPWR 0x1170
> +#define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178
> +#define S5P_CMU_RESET_GPS_LOWPWR 0x117C
> +#define S5P_TOP_BUS_LOWPWR 0x1180
> +#define S5P_TOP_RETENTION_LOWPWR 0x1184
> +#define S5P_TOP_PWR_LOWPWR 0x1188
> +#define S5P_LOGIC_RESET_LOWPWR 0x11A0
> +#define S5P_ONENAND_MEM_LOWPWR 0x11C0
> +#define S5P_G2D_ACP_MEM_LOWPWR 0x11C8
> +#define S5P_USBOTG_MEM_LOWPWR 0x11CC
> +#define S5P_HSMMC_MEM_LOWPWR 0x11D0
> +#define S5P_CSSYS_MEM_LOWPWR 0x11D4
> +#define S5P_SECSS_MEM_LOWPWR 0x11D8
> +#define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200
> +#define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204
> +#define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220
> +#define S5P_PAD_RETENTION_UART_LOWPWR 0x1224
> +#define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228
> +#define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C
> +#define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230
> +#define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234
> +#define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240
> +#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260
> +#define S5P_XUSBXTI_LOWPWR 0x1280
> +#define S5P_XXTI_LOWPWR 0x1284
> +#define S5P_EXT_REGULATOR_LOWPWR 0x12C0
> +#define S5P_GPIO_MODE_LOWPWR 0x1300
> +#define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340
> +#define S5P_CAM_LOWPWR 0x1380
> +#define S5P_TV_LOWPWR 0x1384
> +#define S5P_MFC_LOWPWR 0x1388
> +#define S5P_G3D_LOWPWR 0x138C
> +#define S5P_LCD0_LOWPWR 0x1390
> +#define S5P_MAUDIO_LOWPWR 0x1398
> +#define S5P_GPS_LOWPWR 0x139C
> +#define S5P_GPS_ALIVE_LOWPWR 0x13A0
> +
> +#define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000
> #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
> (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
> #define EXYNOS_ARM_CORE_STATUS(_nr) \
> (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
>
> -#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500)
> +#define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500
> #define EXYNOS_COMMON_CONFIGURATION(_nr) \
> (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
> #define EXYNOS_COMMON_STATUS(_nr) \
> @@ -119,195 +115,195 @@
> #define EXYNOS_COMMON_OPTION(_nr) \
> (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
>
> -#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
> -#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
> -#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
> -#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
> -#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
> -#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
> -#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
> +#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
> +#define S5P_PAD_RET_GPIO_OPTION 0x3108
> +#define S5P_PAD_RET_UART_OPTION 0x3128
> +#define S5P_PAD_RET_MMCA_OPTION 0x3148
> +#define S5P_PAD_RET_MMCB_OPTION 0x3168
> +#define S5P_PAD_RET_EBIA_OPTION 0x3188
> +#define S5P_PAD_RET_EBIB_OPTION 0x31A8
>
> #define S5P_CORE_LOCAL_PWR_EN 0x3
>
> /* Only for EXYNOS4210 */
> -#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
> -#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
> -#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
> -#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
> -#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
> -#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
> +#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
> +#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
> +#define S5P_MODIMIF_MEM_LOWPWR 0x11C4
> +#define S5P_PCIE_MEM_LOWPWR 0x11E0
> +#define S5P_SATA_MEM_LOWPWR 0x11E4
> +#define S5P_LCD1_LOWPWR 0x1394
>
> /* Only for EXYNOS4x12 */
> -#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
> -#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
> -#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
> -#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
> -#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
> -#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
> -#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
> -#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
> -#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
> -#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
> -#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
> -#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
> -#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
> -#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
> -#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
> -#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
> -#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
> -#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
> -#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
> -#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
> -#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
> -#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
> -#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
> -#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
> -#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
> -#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
> -#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
> -#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
> -
> -#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
> -#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
> -#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
> -#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
> -#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
> -#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
> -#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
> -#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
> -#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
> -#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
> +#define S5P_ISP_ARM_LOWPWR 0x1050
> +#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054
> +#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058
> +#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110
> +#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114
> +#define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C
> +#define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130
> +#define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154
> +#define S5P_CMU_RESET_ISP_LOWPWR 0x1174
> +#define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190
> +#define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194
> +#define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198
> +#define S5P_OSCCLK_GATE_LOWPWR 0x11A4
> +#define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0
> +#define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4
> +#define S5P_HSI_MEM_LOWPWR 0x11C4
> +#define S5P_ROTATOR_MEM_LOWPWR 0x11DC
> +#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C
> +#define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250
> +#define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320
> +#define S5P_TOP_ASB_RESET_LOWPWR 0x1344
> +#define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348
> +#define S5P_ISP_LOWPWR 0x1394
> +#define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0
> +#define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4
> +#define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8
> +#define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC
> +#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0
> +
> +#define S5P_ARM_L2_0_OPTION 0x2608
> +#define S5P_ARM_L2_1_OPTION 0x2628
> +#define S5P_ONENAND_MEM_OPTION 0x2E08
> +#define S5P_HSI_MEM_OPTION 0x2E28
> +#define S5P_G2D_ACP_MEM_OPTION 0x2E48
> +#define S5P_USBOTG_MEM_OPTION 0x2E68
> +#define S5P_HSMMC_MEM_OPTION 0x2E88
> +#define S5P_CSSYS_MEM_OPTION 0x2EA8
> +#define S5P_SECSS_MEM_OPTION 0x2EC8
> +#define S5P_ROTATOR_MEM_OPTION 0x2F48
>
> /* Only for EXYNOS4412 */
> -#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
> -#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
> -#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
> -#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
> -#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
> -#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
> +#define S5P_ARM_CORE2_LOWPWR 0x1020
> +#define S5P_DIS_IRQ_CORE2 0x1024
> +#define S5P_DIS_IRQ_CENTRAL2 0x1028
> +#define S5P_ARM_CORE3_LOWPWR 0x1030
> +#define S5P_DIS_IRQ_CORE3 0x1034
> +#define S5P_DIS_IRQ_CENTRAL3 0x1038
>
> /* For EXYNOS5 */
>
> -#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
> -#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
> +#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
> +#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
>
> #define EXYNOS5_SYS_WDTRESET (1 << 20)
>
> -#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
> -#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
> -#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
> -#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
> -#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
> -#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
> -#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
> -#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
> -#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
> -#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
> -#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
> -#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
> -#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
> -#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
> -#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
> -#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
> -#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
> -#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
> -#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
> -#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
> -#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
> -#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
> -#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
> -#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
> -#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
> -#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
> -#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
> -#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
> -#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
> -#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
> -#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
> -#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
> -#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
> -#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
> -#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
> -#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
> -#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
> -#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
> -#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
> -#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
> -#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
> -#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
> -#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
> -#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
> -#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
> -#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
> -#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
> -#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
> -#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
> -#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
> -#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
> -#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
> -#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
> -#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
> -#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
> -#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
> -#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
> -#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
> -#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
> -#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
> -#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
> -#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
> -#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
> -#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
> -#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
> -#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
> -#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
> -#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
> -#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
> -#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
> -#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
> -#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
> -#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
> -#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
> -#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
> -#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
> -#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
> -#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
> -#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
> -#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
> -#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
> -#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
> -#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
> -#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
> -#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
> -#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
> -#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
> -#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
> -#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
> -#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
> -#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
> -#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
> -#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
> -#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
> -#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
> -#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
> -#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
> -#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
> -#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
> -
> -#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
> -#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
> -#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
> -#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
> -#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
> -#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608)
> -#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
> -#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
> -#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
> -#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
> -#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
> -#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
> -#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
> -#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
> -#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
> +#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
> +#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
> +#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
> +#define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010
> +#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
> +#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
> +#define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040
> +#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048
> +#define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050
> +#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
> +#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
> +#define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080
> +#define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0
> +#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
> +#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
> +#define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C
> +#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120
> +#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124
> +#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C
> +#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130
> +#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134
> +#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138
> +#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140
> +#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144
> +#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148
> +#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C
> +#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150
> +#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154
> +#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164
> +#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170
> +#define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180
> +#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184
> +#define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188
> +#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190
> +#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194
> +#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198
> +#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0
> +#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4
> +#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0
> +#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4
> +#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0
> +#define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8
> +#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC
> +#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0
> +#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4
> +#define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8
> +#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC
> +#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0
> +#define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4
> +#define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8
> +#define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC
> +#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4
> +#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
> +#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
> +#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
> +#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208
> +#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
> +#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
> +#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
> +#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
> +#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
> +#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
> +#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238
> +#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C
> +#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240
> +#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250
> +#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260
> +#define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280
> +#define EXYNOS5_XXTI_SYS_PWR_REG 0x1284
> +#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0
> +#define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300
> +#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320
> +#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340
> +#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344
> +#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
> +#define EXYNOS5_GSCL_SYS_PWR_REG 0x1400
> +#define EXYNOS5_ISP_SYS_PWR_REG 0x1404
> +#define EXYNOS5_MFC_SYS_PWR_REG 0x1408
> +#define EXYNOS5_G3D_SYS_PWR_REG 0x140C
> +#define EXYNOS5_DISP1_SYS_PWR_REG 0x1414
> +#define EXYNOS5_MAU_SYS_PWR_REG 0x1418
> +#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480
> +#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484
> +#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488
> +#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C
> +#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494
> +#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498
> +#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0
> +#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4
> +#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8
> +#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC
> +#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4
> +#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8
> +#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580
> +#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584
> +#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588
> +#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C
> +#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594
> +#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598
> +
> +#define EXYNOS5_ARM_CORE0_OPTION 0x2008
> +#define EXYNOS5_ARM_CORE1_OPTION 0x2088
> +#define EXYNOS5_FSYS_ARM_OPTION 0x2208
> +#define EXYNOS5_ISP_ARM_OPTION 0x2288
> +#define EXYNOS5_ARM_COMMON_OPTION 0x2408
> +#define EXYNOS5_ARM_L2_OPTION 0x2608
> +#define EXYNOS5_TOP_PWR_OPTION 0x2C48
> +#define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8
> +#define EXYNOS5_JPEG_MEM_OPTION 0x2F48
> +#define EXYNOS5_GSCL_OPTION 0x4008
> +#define EXYNOS5_ISP_OPTION 0x4028
> +#define EXYNOS5_MFC_OPTION 0x4048
> +#define EXYNOS5_G3D_OPTION 0x4068
> +#define EXYNOS5_DISP1_OPTION 0x40A8
> +#define EXYNOS5_MAU_OPTION 0x40C8
>
> #define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
> #define EXYNOS5_USE_SC_COUNTER (1 << 0)
> diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-
> s5p.h
> index c186786..f5b9d3f 100644
> --- a/arch/arm/plat-samsung/include/plat/map-s5p.h
> +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
> @@ -15,7 +15,6 @@
>
> #define S5P_VA_CHIPID S3C_ADDR(0x02000000)
> #define S5P_VA_CMU S3C_ADDR(0x02100000)
> -#define S5P_VA_PMU S3C_ADDR(0x02180000)
> #define S5P_VA_GPIO S3C_ADDR(0x02200000)
> #define S5P_VA_GPIO1 S5P_VA_GPIO
> #define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
> --
> 1.7.9.5
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v7 0/4] ARM: Exynos: PMU cleanup and refactoring for using DT
2014-07-09 4:00 ` Pankaj Dubey
(?)
@ 2014-07-11 6:10 ` Naveen Krishna Ch
-1 siblings, 0 replies; 35+ messages in thread
From: Naveen Krishna Ch @ 2014-07-11 6:10 UTC (permalink / raw)
To: Pankaj Dubey
Cc: linux-arm-kernel, linux-samsung-soc, linux-kernel, Kukjin Kim,
Russell King - ARM Linux, t.figa, vikas.sajjan, joshi, naushad,
Thomas Abraham, chow.kim
Hello Pankaj,
On 9 July 2014 09:30, Pankaj Dubey <pankaj.dubey@samsung.com> wrote:
> This patch series, modifies Exynos Power Management Unit (PMU) related code
> for converting it into a platform_driver. This is also preparation for moving
> PMU related code out of machine folder into a either "drivers/mfd", or
> "drivers/power" or some other suitable place so that ARM64 based SoC can
> utilize common piece of code.
>
> These patches are created on top of Kukjin Kim's for-next.
> I have tested this patches on Exynos5250 Snow board for system boot and S2R.
>
> This patch series depends on following two patch series:
> [1]: mfd: syscon: Decouple syscon interface from syscon devices.
> https://lkml.org/lkml/2014/6/24/188
>
> [2]: Cleanup patches for mach-exynos.
> http://www.spinics.net/lists/arm-kernel/msg341474.html
With the above mentioned patches + this series
I was able to add PMU registers using syscon in the DTS node for DP and ADC.
and access the PMU registers in the respective drivers using syscon API.
Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>
> Patch v6 and discussion can be found here:
> https://lkml.org/lkml/2014/7/7/22
>
> Change since v6:
> - Removed NULL check for pmu_data in pmu.c.
> - Moved pmu_raw_readl and pmu_raw_writel inline helper function
> into common.h.
>
> Change Since v5:
> - Squashed patch "Move "mach/map.h" inclusion from regs-pmu.h to platsmp.c"
> into patch "Refactored code for using PMU address via DT".
> - Addressed review comments from Tomasz Figa.
> - Using init_irq machine function to initialize PMU mapping instead
> of init_time.
> - Rebased on latest Kukjin Kim's for-next branch.
>
> Changes Since v4:
> - Splitted patch series in two parts. Part 1 has code cleanup under mach-exynos
> and posted as separate patch [2]. Current patchset is part 2 which modified
> exynos pmu implementation for making it platform driver.
> - Removed dependency over early_syscon API.
> - Removed usage of regmap read/write APIs.
> - Modified probe function to register exynos pmu as syscon provider using
> Tomasz Figa's syscon patch [1].
> - Address various other review comments from Tomasz Figa.
> - Removed signed-off-by of Young-Gun Jang <yg1004.jang@samsung.com>,
> as this id is no more valid. Taking ownership of all his patches.
>
> Changes Since v3:
> - Optimized exynos_pmu_probe function by removing exynos_pmu_data_init
> as suggested by Vikas Sajjan.
> - Modified syscon_early_regmap_lookup_by_phandle and
> syscon_regmap_lookup_by_phandle function call to pass property as NULL.
>
> Changes Since v2:
> - Rebased on top of Daniel Lezcano's Exynos cpuidle refactor patches.
> - Removed early mapping of PMU base address from exynos.c and removed
> "get_exynos_pmuaddr" function. Instead of this added code in platsmp.c
> to get PMU base address using of_iomap as suggested by Tomasz Figa.
> - Converted PMU implementation into platform_driver by using static
> platform_device method.
>
> Changes Since v1:
> - Rebased on latest for-next of Kukjin Kim's tree.
> - Updated patch: Add support for mapping PMU base address via DT
> - Removed __initdata from declaration of "exynos_pmu_base", as it caused
> kernel crash as pointed out by Vikas Sajjan.
> - Added support for Syscon initialization and getting PMU regmap handle
> as suggested by Sylwester. Since current implementation of early
> intialization [1] has limitation that "early_syscon_init" requires
> DT to be unflattened and system should be able to allocate memory,
> we can't use regmap handles for platsmp.c file as "smp_secondary_init"
> will be called before DT unflattening. So I have kept both method for
> accessing PMU base address. platsmp.c will use ioremmaped address where
> as rest other files can use regmap handle.
> - Updated patch: Refactored code for PMU register mapping via DT
> - Modified to use regmap_read/write when using regmap handle.
> - Added patch: Add device tree based initialization support for PMU.
> - Convert existing PMU implementation to be a device tree based
> before moving it to "drivers/mfd" folder. As suggested by Bartlomiej.
> - Dropped making a platform_driver for PMU, as currently PMU binding
> has two compatibility strings as "samsung, exynosxxx-pmu", "syscon",
> once we enable MFD_SYSCON config option, current "syscon" driver probe
> gets called and PMU probe never gets called. So modified PMU
> initialization code to scan DT and match against supported compatiblity
> string in driver code, and once we get matching node use that for
> accessing PMU regmap handle using "syscon_early_regmap_lookup_by_phandle".
> If there is any better solution please suggest.
>
>
> Pankaj Dubey (4):
> ARM: EXYNOS: Add support for mapping PMU base address via DT
> ARM: EXYNOS: Refactored code for using PMU address via DT
> ARM: EXYNOS: Add platform driver support for Exynos PMU
> ARM: EXYNOS: Move PMU specific definitions from common.h
>
> arch/arm/mach-exynos/Kconfig | 1 +
> arch/arm/mach-exynos/common.h | 28 +-
> arch/arm/mach-exynos/exynos-pmu.h | 24 ++
> arch/arm/mach-exynos/exynos.c | 49 ++-
> arch/arm/mach-exynos/include/mach/map.h | 3 -
> arch/arm/mach-exynos/mcpm-exynos.c | 8 +-
> arch/arm/mach-exynos/platsmp.c | 4 +-
> arch/arm/mach-exynos/pm.c | 77 ++--
> arch/arm/mach-exynos/pmu.c | 225 ++++++++---
> arch/arm/mach-exynos/regs-pmu.h | 522 +++++++++++++-------------
> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 -
> 11 files changed, 555 insertions(+), 387 deletions(-)
> create mode 100644 arch/arm/mach-exynos/exynos-pmu.h
>
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Shine bright,
(: Nav :)
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v7 0/4] ARM: Exynos: PMU cleanup and refactoring for using DT
@ 2014-07-11 6:10 ` Naveen Krishna Ch
0 siblings, 0 replies; 35+ messages in thread
From: Naveen Krishna Ch @ 2014-07-11 6:10 UTC (permalink / raw)
To: Pankaj Dubey
Cc: linux-arm-kernel, linux-samsung-soc, linux-kernel, Kukjin Kim,
Russell King - ARM Linux, t.figa, vikas.sajjan, joshi, naushad,
Thomas Abraham, chow.kim
Hello Pankaj,
On 9 July 2014 09:30, Pankaj Dubey <pankaj.dubey@samsung.com> wrote:
> This patch series, modifies Exynos Power Management Unit (PMU) related code
> for converting it into a platform_driver. This is also preparation for moving
> PMU related code out of machine folder into a either "drivers/mfd", or
> "drivers/power" or some other suitable place so that ARM64 based SoC can
> utilize common piece of code.
>
> These patches are created on top of Kukjin Kim's for-next.
> I have tested this patches on Exynos5250 Snow board for system boot and S2R.
>
> This patch series depends on following two patch series:
> [1]: mfd: syscon: Decouple syscon interface from syscon devices.
> https://lkml.org/lkml/2014/6/24/188
>
> [2]: Cleanup patches for mach-exynos.
> http://www.spinics.net/lists/arm-kernel/msg341474.html
With the above mentioned patches + this series
I was able to add PMU registers using syscon in the DTS node for DP and ADC.
and access the PMU registers in the respective drivers using syscon API.
Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>
> Patch v6 and discussion can be found here:
> https://lkml.org/lkml/2014/7/7/22
>
> Change since v6:
> - Removed NULL check for pmu_data in pmu.c.
> - Moved pmu_raw_readl and pmu_raw_writel inline helper function
> into common.h.
>
> Change Since v5:
> - Squashed patch "Move "mach/map.h" inclusion from regs-pmu.h to platsmp.c"
> into patch "Refactored code for using PMU address via DT".
> - Addressed review comments from Tomasz Figa.
> - Using init_irq machine function to initialize PMU mapping instead
> of init_time.
> - Rebased on latest Kukjin Kim's for-next branch.
>
> Changes Since v4:
> - Splitted patch series in two parts. Part 1 has code cleanup under mach-exynos
> and posted as separate patch [2]. Current patchset is part 2 which modified
> exynos pmu implementation for making it platform driver.
> - Removed dependency over early_syscon API.
> - Removed usage of regmap read/write APIs.
> - Modified probe function to register exynos pmu as syscon provider using
> Tomasz Figa's syscon patch [1].
> - Address various other review comments from Tomasz Figa.
> - Removed signed-off-by of Young-Gun Jang <yg1004.jang@samsung.com>,
> as this id is no more valid. Taking ownership of all his patches.
>
> Changes Since v3:
> - Optimized exynos_pmu_probe function by removing exynos_pmu_data_init
> as suggested by Vikas Sajjan.
> - Modified syscon_early_regmap_lookup_by_phandle and
> syscon_regmap_lookup_by_phandle function call to pass property as NULL.
>
> Changes Since v2:
> - Rebased on top of Daniel Lezcano's Exynos cpuidle refactor patches.
> - Removed early mapping of PMU base address from exynos.c and removed
> "get_exynos_pmuaddr" function. Instead of this added code in platsmp.c
> to get PMU base address using of_iomap as suggested by Tomasz Figa.
> - Converted PMU implementation into platform_driver by using static
> platform_device method.
>
> Changes Since v1:
> - Rebased on latest for-next of Kukjin Kim's tree.
> - Updated patch: Add support for mapping PMU base address via DT
> - Removed __initdata from declaration of "exynos_pmu_base", as it caused
> kernel crash as pointed out by Vikas Sajjan.
> - Added support for Syscon initialization and getting PMU regmap handle
> as suggested by Sylwester. Since current implementation of early
> intialization [1] has limitation that "early_syscon_init" requires
> DT to be unflattened and system should be able to allocate memory,
> we can't use regmap handles for platsmp.c file as "smp_secondary_init"
> will be called before DT unflattening. So I have kept both method for
> accessing PMU base address. platsmp.c will use ioremmaped address where
> as rest other files can use regmap handle.
> - Updated patch: Refactored code for PMU register mapping via DT
> - Modified to use regmap_read/write when using regmap handle.
> - Added patch: Add device tree based initialization support for PMU.
> - Convert existing PMU implementation to be a device tree based
> before moving it to "drivers/mfd" folder. As suggested by Bartlomiej.
> - Dropped making a platform_driver for PMU, as currently PMU binding
> has two compatibility strings as "samsung, exynosxxx-pmu", "syscon",
> once we enable MFD_SYSCON config option, current "syscon" driver probe
> gets called and PMU probe never gets called. So modified PMU
> initialization code to scan DT and match against supported compatiblity
> string in driver code, and once we get matching node use that for
> accessing PMU regmap handle using "syscon_early_regmap_lookup_by_phandle".
> If there is any better solution please suggest.
>
>
> Pankaj Dubey (4):
> ARM: EXYNOS: Add support for mapping PMU base address via DT
> ARM: EXYNOS: Refactored code for using PMU address via DT
> ARM: EXYNOS: Add platform driver support for Exynos PMU
> ARM: EXYNOS: Move PMU specific definitions from common.h
>
> arch/arm/mach-exynos/Kconfig | 1 +
> arch/arm/mach-exynos/common.h | 28 +-
> arch/arm/mach-exynos/exynos-pmu.h | 24 ++
> arch/arm/mach-exynos/exynos.c | 49 ++-
> arch/arm/mach-exynos/include/mach/map.h | 3 -
> arch/arm/mach-exynos/mcpm-exynos.c | 8 +-
> arch/arm/mach-exynos/platsmp.c | 4 +-
> arch/arm/mach-exynos/pm.c | 77 ++--
> arch/arm/mach-exynos/pmu.c | 225 ++++++++---
> arch/arm/mach-exynos/regs-pmu.h | 522 +++++++++++++-------------
> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 -
> 11 files changed, 555 insertions(+), 387 deletions(-)
> create mode 100644 arch/arm/mach-exynos/exynos-pmu.h
>
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Shine bright,
(: Nav :)
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 0/4] ARM: Exynos: PMU cleanup and refactoring for using DT
@ 2014-07-11 6:10 ` Naveen Krishna Ch
0 siblings, 0 replies; 35+ messages in thread
From: Naveen Krishna Ch @ 2014-07-11 6:10 UTC (permalink / raw)
To: linux-arm-kernel
Hello Pankaj,
On 9 July 2014 09:30, Pankaj Dubey <pankaj.dubey@samsung.com> wrote:
> This patch series, modifies Exynos Power Management Unit (PMU) related code
> for converting it into a platform_driver. This is also preparation for moving
> PMU related code out of machine folder into a either "drivers/mfd", or
> "drivers/power" or some other suitable place so that ARM64 based SoC can
> utilize common piece of code.
>
> These patches are created on top of Kukjin Kim's for-next.
> I have tested this patches on Exynos5250 Snow board for system boot and S2R.
>
> This patch series depends on following two patch series:
> [1]: mfd: syscon: Decouple syscon interface from syscon devices.
> https://lkml.org/lkml/2014/6/24/188
>
> [2]: Cleanup patches for mach-exynos.
> http://www.spinics.net/lists/arm-kernel/msg341474.html
With the above mentioned patches + this series
I was able to add PMU registers using syscon in the DTS node for DP and ADC.
and access the PMU registers in the respective drivers using syscon API.
Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>
> Patch v6 and discussion can be found here:
> https://lkml.org/lkml/2014/7/7/22
>
> Change since v6:
> - Removed NULL check for pmu_data in pmu.c.
> - Moved pmu_raw_readl and pmu_raw_writel inline helper function
> into common.h.
>
> Change Since v5:
> - Squashed patch "Move "mach/map.h" inclusion from regs-pmu.h to platsmp.c"
> into patch "Refactored code for using PMU address via DT".
> - Addressed review comments from Tomasz Figa.
> - Using init_irq machine function to initialize PMU mapping instead
> of init_time.
> - Rebased on latest Kukjin Kim's for-next branch.
>
> Changes Since v4:
> - Splitted patch series in two parts. Part 1 has code cleanup under mach-exynos
> and posted as separate patch [2]. Current patchset is part 2 which modified
> exynos pmu implementation for making it platform driver.
> - Removed dependency over early_syscon API.
> - Removed usage of regmap read/write APIs.
> - Modified probe function to register exynos pmu as syscon provider using
> Tomasz Figa's syscon patch [1].
> - Address various other review comments from Tomasz Figa.
> - Removed signed-off-by of Young-Gun Jang <yg1004.jang@samsung.com>,
> as this id is no more valid. Taking ownership of all his patches.
>
> Changes Since v3:
> - Optimized exynos_pmu_probe function by removing exynos_pmu_data_init
> as suggested by Vikas Sajjan.
> - Modified syscon_early_regmap_lookup_by_phandle and
> syscon_regmap_lookup_by_phandle function call to pass property as NULL.
>
> Changes Since v2:
> - Rebased on top of Daniel Lezcano's Exynos cpuidle refactor patches.
> - Removed early mapping of PMU base address from exynos.c and removed
> "get_exynos_pmuaddr" function. Instead of this added code in platsmp.c
> to get PMU base address using of_iomap as suggested by Tomasz Figa.
> - Converted PMU implementation into platform_driver by using static
> platform_device method.
>
> Changes Since v1:
> - Rebased on latest for-next of Kukjin Kim's tree.
> - Updated patch: Add support for mapping PMU base address via DT
> - Removed __initdata from declaration of "exynos_pmu_base", as it caused
> kernel crash as pointed out by Vikas Sajjan.
> - Added support for Syscon initialization and getting PMU regmap handle
> as suggested by Sylwester. Since current implementation of early
> intialization [1] has limitation that "early_syscon_init" requires
> DT to be unflattened and system should be able to allocate memory,
> we can't use regmap handles for platsmp.c file as "smp_secondary_init"
> will be called before DT unflattening. So I have kept both method for
> accessing PMU base address. platsmp.c will use ioremmaped address where
> as rest other files can use regmap handle.
> - Updated patch: Refactored code for PMU register mapping via DT
> - Modified to use regmap_read/write when using regmap handle.
> - Added patch: Add device tree based initialization support for PMU.
> - Convert existing PMU implementation to be a device tree based
> before moving it to "drivers/mfd" folder. As suggested by Bartlomiej.
> - Dropped making a platform_driver for PMU, as currently PMU binding
> has two compatibility strings as "samsung, exynosxxx-pmu", "syscon",
> once we enable MFD_SYSCON config option, current "syscon" driver probe
> gets called and PMU probe never gets called. So modified PMU
> initialization code to scan DT and match against supported compatiblity
> string in driver code, and once we get matching node use that for
> accessing PMU regmap handle using "syscon_early_regmap_lookup_by_phandle".
> If there is any better solution please suggest.
>
>
> Pankaj Dubey (4):
> ARM: EXYNOS: Add support for mapping PMU base address via DT
> ARM: EXYNOS: Refactored code for using PMU address via DT
> ARM: EXYNOS: Add platform driver support for Exynos PMU
> ARM: EXYNOS: Move PMU specific definitions from common.h
>
> arch/arm/mach-exynos/Kconfig | 1 +
> arch/arm/mach-exynos/common.h | 28 +-
> arch/arm/mach-exynos/exynos-pmu.h | 24 ++
> arch/arm/mach-exynos/exynos.c | 49 ++-
> arch/arm/mach-exynos/include/mach/map.h | 3 -
> arch/arm/mach-exynos/mcpm-exynos.c | 8 +-
> arch/arm/mach-exynos/platsmp.c | 4 +-
> arch/arm/mach-exynos/pm.c | 77 ++--
> arch/arm/mach-exynos/pmu.c | 225 ++++++++---
> arch/arm/mach-exynos/regs-pmu.h | 522 +++++++++++++-------------
> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 -
> 11 files changed, 555 insertions(+), 387 deletions(-)
> create mode 100644 arch/arm/mach-exynos/exynos-pmu.h
>
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
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(: Nav :)
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
2014-07-09 4:00 ` Pankaj Dubey
@ 2014-07-25 4:04 ` Kukjin Kim
-1 siblings, 0 replies; 35+ messages in thread
From: Kukjin Kim @ 2014-07-25 4:04 UTC (permalink / raw)
To: 'Pankaj Dubey',
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: linux, t.figa, vikas.sajjan, joshi, naushad, thomas.ab, chow.kim
Pankaj Dubey wrote:
>
> This patch modifies Exynos Power Management Unit (PMU) initialization
> implementation in following way:
>
> - Added platform driver support and probe function where Exynos PMU
> driver will register itself as syscon provider with syscon framework.
> - Added platform struct exynos_pmu_data to hold platform specific data.
> - For each SoC's PMU support now we can add platform data and statically
> bind PMU configuration and SoC specific initialization function.
> - Separate each SoC's PMU initialization function and make it as part of
> platform data.
> - It also removes uses of soc_is_exynosXYZ().
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> ---
> arch/arm/mach-exynos/Kconfig | 1 +
> arch/arm/mach-exynos/pmu.c | 185 +++++++++++++++++++++++++++++++++---------
> 2 files changed, 146 insertions(+), 40 deletions(-)
>
Looks good to me, will apply this and 4/4.
Thanks,
Kukjin
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 8f9b66c..a2944ac 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -24,6 +24,7 @@ menuconfig ARCH_EXYNOS
> select PM_GENERIC_DOMAINS if PM_RUNTIME
> select S5P_DEV_MFC
> select SRAM
> + select MFD_SYSCON
> help
> Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
>
> diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
> index ff9d23f..5b76728 100644
> --- a/arch/arm/mach-exynos/pmu.c
> +++ b/arch/arm/mach-exynos/pmu.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
> + * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
> * http://www.samsung.com/
> *
> * EXYNOS - CPU PMU(Power Management Unit) support
> @@ -10,12 +10,28 @@
> */
>
> #include <linux/io.h>
> -#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
>
> #include "common.h"
> #include "regs-pmu.h"
>
> -static const struct exynos_pmu_conf *exynos_pmu_config;
> +struct exynos_pmu_data {
> + const struct exynos_pmu_conf *pmu_config;
> + const struct exynos_pmu_conf *pmu_config_extra;
> +
> + void (*pmu_init)(void);
> + void (*powerdown_conf)(enum sys_powerdown);
> +};
> +
> +struct exynos_pmu_context {
> + struct device *dev;
> + const struct exynos_pmu_data *pmu_data;
> +};
> +
> +static struct exynos_pmu_context *pmu_context;
>
> static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
> /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
> @@ -335,7 +351,7 @@ static unsigned int const exynos5_list_diable_wfi_wfe[] = {
> EXYNOS5_ISP_ARM_OPTION,
> };
>
> -static void exynos5_init_pmu(void)
> +static void exynos5_powerdown_conf(enum sys_powerdown mode)
> {
> unsigned int i;
> unsigned int tmp;
> @@ -372,51 +388,140 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
> {
> unsigned int i;
>
> - if (soc_is_exynos5250())
> - exynos5_init_pmu();
> + const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
>
> - for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
> - pmu_raw_writel(exynos_pmu_config[i].val[mode],
> - exynos_pmu_config[i].offset);
> + if (pmu_data->powerdown_conf)
> + pmu_data->powerdown_conf(mode);
>
> - if (soc_is_exynos4412()) {
> - for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
> - pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
> - exynos4412_pmu_config[i].offset);
> + if (pmu_data->pmu_config) {
> + for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END) ; i++)
> + pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
> + pmu_data->pmu_config[i].offset);
> + }
> +
> + if (pmu_data->pmu_config_extra) {
> + for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
> + pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
> + pmu_data->pmu_config_extra[i].offset);
> }
> }
>
> -static int __init exynos_pmu_init(void)
> +static void exynos5250_pmu_init(void)
> {
> unsigned int value;
> + /*
> + * When SYS_WDTRESET is set, watchdog timer reset request
> + * is ignored by power management unit.
> + */
> + value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> + value &= ~EXYNOS5_SYS_WDTRESET;
> + pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
> +
> + value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> + value &= ~EXYNOS5_SYS_WDTRESET;
> + pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
> +}
> +
> +static const struct exynos_pmu_data exynos4210_pmu_data = {
> + .pmu_config = exynos4210_pmu_config,
> +};
> +
> +static const struct exynos_pmu_data exynos4212_pmu_data = {
> + .pmu_config = exynos4x12_pmu_config,
> +};
> +
> +static const struct exynos_pmu_data exynos4412_pmu_data = {
> + .pmu_config = exynos4x12_pmu_config,
> + .pmu_config_extra = exynos4412_pmu_config,
> +};
> +
> +static const struct exynos_pmu_data exynos5250_pmu_data = {
> + .pmu_config = exynos5250_pmu_config,
> + .pmu_init = exynos5250_pmu_init,
> + .powerdown_conf = exynos5_powerdown_conf,
> +};
> +
> +static const struct regmap_config pmu_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
>
> - exynos_pmu_config = exynos4210_pmu_config;
> -
> - if (soc_is_exynos4210()) {
> - exynos_pmu_config = exynos4210_pmu_config;
> - pr_info("EXYNOS4210 PMU Initialize\n");
> - } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
> - exynos_pmu_config = exynos4x12_pmu_config;
> - pr_info("EXYNOS4x12 PMU Initialize\n");
> - } else if (soc_is_exynos5250()) {
> - /*
> - * When SYS_WDTRESET is set, watchdog timer reset request
> - * is ignored by power management unit.
> - */
> - value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> - value &= ~EXYNOS5_SYS_WDTRESET;
> - pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
> -
> - value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> - value &= ~EXYNOS5_SYS_WDTRESET;
> - pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
> -
> - exynos_pmu_config = exynos5250_pmu_config;
> - pr_info("EXYNOS5250 PMU Initialize\n");
> - } else {
> - pr_info("EXYNOS: PMU not supported\n");
> +/*
> + * PMU platform driver and devicetree bindings.
> + */
> +static const struct of_device_id exynos_pmu_of_device_ids[] = {
> + {
> + .compatible = "samsung,exynos4210-pmu",
> + .data = &exynos4210_pmu_data,
> + }, {
> + .compatible = "samsung,exynos4212-pmu",
> + .data = &exynos4212_pmu_data,
> + }, {
> + .compatible = "samsung,exynos4412-pmu",
> + .data = &exynos4412_pmu_data,
> + }, {
> + .compatible = "samsung,exynos5250-pmu",
> + .data = &exynos5250_pmu_data,
> + },
> + { /*sentinel*/ },
> +};
> +
> +static int exynos_pmu_probe(struct platform_device *pdev)
> +{
> + const struct of_device_id *match;
> + struct device *dev = &pdev->dev;
> + struct regmap *regmap;
> + struct resource *res;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + pmu_base_addr = devm_ioremap_resource(dev, res);
> + if (IS_ERR(pmu_base_addr))
> + return PTR_ERR(pmu_base_addr);
> +
> + pmu_context = devm_kzalloc(&pdev->dev,
> + sizeof(struct exynos_pmu_context),
> + GFP_KERNEL);
> + if (!pmu_context) {
> + dev_err(dev, "Cannot allocate memory.\n");
> + return -ENOMEM;
> + }
> + pmu_context->dev = dev;
> +
> + regmap = devm_regmap_init_mmio(dev, pmu_base_addr,
> + &pmu_regmap_config);
> + if (IS_ERR(regmap)) {
> + dev_err(dev, "regmap init failed\n");
> + return PTR_ERR(regmap);
> }
>
> + devm_syscon_register(dev, regmap);
> +
> + match = of_match_node(exynos_pmu_of_device_ids, pdev->dev.of_node);
> +
> + pmu_context->pmu_data = match->data;
> +
> + if (pmu_context->pmu_data->pmu_init)
> + pmu_context->pmu_data->pmu_init();
> +
> + platform_set_drvdata(pdev, pmu_context);
> +
> + dev_dbg(dev, "Exynos PMU Driver probe done\n");
> return 0;
> }
> -arch_initcall(exynos_pmu_init);
> +
> +static struct platform_driver exynos_pmu_driver = {
> + .driver = {
> + .name = "exynos-pmu",
> + .owner = THIS_MODULE,
> + .of_match_table = exynos_pmu_of_device_ids,
> + },
> + .probe = exynos_pmu_probe,
> +};
> +
> +static int __init exynos_pmu_init(void)
> +{
> + return platform_driver_register(&exynos_pmu_driver);
> +
> +}
> +postcore_initcall(exynos_pmu_init);
> --
> 1.7.9.5
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
@ 2014-07-25 4:04 ` Kukjin Kim
0 siblings, 0 replies; 35+ messages in thread
From: Kukjin Kim @ 2014-07-25 4:04 UTC (permalink / raw)
To: linux-arm-kernel
Pankaj Dubey wrote:
>
> This patch modifies Exynos Power Management Unit (PMU) initialization
> implementation in following way:
>
> - Added platform driver support and probe function where Exynos PMU
> driver will register itself as syscon provider with syscon framework.
> - Added platform struct exynos_pmu_data to hold platform specific data.
> - For each SoC's PMU support now we can add platform data and statically
> bind PMU configuration and SoC specific initialization function.
> - Separate each SoC's PMU initialization function and make it as part of
> platform data.
> - It also removes uses of soc_is_exynosXYZ().
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> ---
> arch/arm/mach-exynos/Kconfig | 1 +
> arch/arm/mach-exynos/pmu.c | 185 +++++++++++++++++++++++++++++++++---------
> 2 files changed, 146 insertions(+), 40 deletions(-)
>
Looks good to me, will apply this and 4/4.
Thanks,
Kukjin
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 8f9b66c..a2944ac 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -24,6 +24,7 @@ menuconfig ARCH_EXYNOS
> select PM_GENERIC_DOMAINS if PM_RUNTIME
> select S5P_DEV_MFC
> select SRAM
> + select MFD_SYSCON
> help
> Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
>
> diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
> index ff9d23f..5b76728 100644
> --- a/arch/arm/mach-exynos/pmu.c
> +++ b/arch/arm/mach-exynos/pmu.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
> + * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
> * http://www.samsung.com/
> *
> * EXYNOS - CPU PMU(Power Management Unit) support
> @@ -10,12 +10,28 @@
> */
>
> #include <linux/io.h>
> -#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
>
> #include "common.h"
> #include "regs-pmu.h"
>
> -static const struct exynos_pmu_conf *exynos_pmu_config;
> +struct exynos_pmu_data {
> + const struct exynos_pmu_conf *pmu_config;
> + const struct exynos_pmu_conf *pmu_config_extra;
> +
> + void (*pmu_init)(void);
> + void (*powerdown_conf)(enum sys_powerdown);
> +};
> +
> +struct exynos_pmu_context {
> + struct device *dev;
> + const struct exynos_pmu_data *pmu_data;
> +};
> +
> +static struct exynos_pmu_context *pmu_context;
>
> static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
> /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
> @@ -335,7 +351,7 @@ static unsigned int const exynos5_list_diable_wfi_wfe[] = {
> EXYNOS5_ISP_ARM_OPTION,
> };
>
> -static void exynos5_init_pmu(void)
> +static void exynos5_powerdown_conf(enum sys_powerdown mode)
> {
> unsigned int i;
> unsigned int tmp;
> @@ -372,51 +388,140 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
> {
> unsigned int i;
>
> - if (soc_is_exynos5250())
> - exynos5_init_pmu();
> + const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
>
> - for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
> - pmu_raw_writel(exynos_pmu_config[i].val[mode],
> - exynos_pmu_config[i].offset);
> + if (pmu_data->powerdown_conf)
> + pmu_data->powerdown_conf(mode);
>
> - if (soc_is_exynos4412()) {
> - for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
> - pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
> - exynos4412_pmu_config[i].offset);
> + if (pmu_data->pmu_config) {
> + for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END) ; i++)
> + pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
> + pmu_data->pmu_config[i].offset);
> + }
> +
> + if (pmu_data->pmu_config_extra) {
> + for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
> + pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
> + pmu_data->pmu_config_extra[i].offset);
> }
> }
>
> -static int __init exynos_pmu_init(void)
> +static void exynos5250_pmu_init(void)
> {
> unsigned int value;
> + /*
> + * When SYS_WDTRESET is set, watchdog timer reset request
> + * is ignored by power management unit.
> + */
> + value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> + value &= ~EXYNOS5_SYS_WDTRESET;
> + pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
> +
> + value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> + value &= ~EXYNOS5_SYS_WDTRESET;
> + pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
> +}
> +
> +static const struct exynos_pmu_data exynos4210_pmu_data = {
> + .pmu_config = exynos4210_pmu_config,
> +};
> +
> +static const struct exynos_pmu_data exynos4212_pmu_data = {
> + .pmu_config = exynos4x12_pmu_config,
> +};
> +
> +static const struct exynos_pmu_data exynos4412_pmu_data = {
> + .pmu_config = exynos4x12_pmu_config,
> + .pmu_config_extra = exynos4412_pmu_config,
> +};
> +
> +static const struct exynos_pmu_data exynos5250_pmu_data = {
> + .pmu_config = exynos5250_pmu_config,
> + .pmu_init = exynos5250_pmu_init,
> + .powerdown_conf = exynos5_powerdown_conf,
> +};
> +
> +static const struct regmap_config pmu_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
>
> - exynos_pmu_config = exynos4210_pmu_config;
> -
> - if (soc_is_exynos4210()) {
> - exynos_pmu_config = exynos4210_pmu_config;
> - pr_info("EXYNOS4210 PMU Initialize\n");
> - } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
> - exynos_pmu_config = exynos4x12_pmu_config;
> - pr_info("EXYNOS4x12 PMU Initialize\n");
> - } else if (soc_is_exynos5250()) {
> - /*
> - * When SYS_WDTRESET is set, watchdog timer reset request
> - * is ignored by power management unit.
> - */
> - value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> - value &= ~EXYNOS5_SYS_WDTRESET;
> - pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
> -
> - value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> - value &= ~EXYNOS5_SYS_WDTRESET;
> - pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
> -
> - exynos_pmu_config = exynos5250_pmu_config;
> - pr_info("EXYNOS5250 PMU Initialize\n");
> - } else {
> - pr_info("EXYNOS: PMU not supported\n");
> +/*
> + * PMU platform driver and devicetree bindings.
> + */
> +static const struct of_device_id exynos_pmu_of_device_ids[] = {
> + {
> + .compatible = "samsung,exynos4210-pmu",
> + .data = &exynos4210_pmu_data,
> + }, {
> + .compatible = "samsung,exynos4212-pmu",
> + .data = &exynos4212_pmu_data,
> + }, {
> + .compatible = "samsung,exynos4412-pmu",
> + .data = &exynos4412_pmu_data,
> + }, {
> + .compatible = "samsung,exynos5250-pmu",
> + .data = &exynos5250_pmu_data,
> + },
> + { /*sentinel*/ },
> +};
> +
> +static int exynos_pmu_probe(struct platform_device *pdev)
> +{
> + const struct of_device_id *match;
> + struct device *dev = &pdev->dev;
> + struct regmap *regmap;
> + struct resource *res;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + pmu_base_addr = devm_ioremap_resource(dev, res);
> + if (IS_ERR(pmu_base_addr))
> + return PTR_ERR(pmu_base_addr);
> +
> + pmu_context = devm_kzalloc(&pdev->dev,
> + sizeof(struct exynos_pmu_context),
> + GFP_KERNEL);
> + if (!pmu_context) {
> + dev_err(dev, "Cannot allocate memory.\n");
> + return -ENOMEM;
> + }
> + pmu_context->dev = dev;
> +
> + regmap = devm_regmap_init_mmio(dev, pmu_base_addr,
> + &pmu_regmap_config);
> + if (IS_ERR(regmap)) {
> + dev_err(dev, "regmap init failed\n");
> + return PTR_ERR(regmap);
> }
>
> + devm_syscon_register(dev, regmap);
> +
> + match = of_match_node(exynos_pmu_of_device_ids, pdev->dev.of_node);
> +
> + pmu_context->pmu_data = match->data;
> +
> + if (pmu_context->pmu_data->pmu_init)
> + pmu_context->pmu_data->pmu_init();
> +
> + platform_set_drvdata(pdev, pmu_context);
> +
> + dev_dbg(dev, "Exynos PMU Driver probe done\n");
> return 0;
> }
> -arch_initcall(exynos_pmu_init);
> +
> +static struct platform_driver exynos_pmu_driver = {
> + .driver = {
> + .name = "exynos-pmu",
> + .owner = THIS_MODULE,
> + .of_match_table = exynos_pmu_of_device_ids,
> + },
> + .probe = exynos_pmu_probe,
> +};
> +
> +static int __init exynos_pmu_init(void)
> +{
> + return platform_driver_register(&exynos_pmu_driver);
> +
> +}
> +postcore_initcall(exynos_pmu_init);
> --
> 1.7.9.5
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
2014-07-25 4:04 ` Kukjin Kim
@ 2014-07-25 5:32 ` Pankaj Dubey
-1 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-25 5:32 UTC (permalink / raw)
To: 'Kukjin Kim', linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: linux, t.figa, vikas.sajjan, joshi, naushad, thomas.ab, chow.kim
Hi Kukjin,
On Friday, July 25, 2014 Kukjin Kim wrote:
> Subject: RE: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for
> Exynos PMU
>
> Pankaj Dubey wrote:
> >
> > This patch modifies Exynos Power Management Unit (PMU) initialization
> > implementation in following way:
> >
> > - Added platform driver support and probe function where Exynos PMU
> > driver will register itself as syscon provider with syscon framework.
> > - Added platform struct exynos_pmu_data to hold platform specific data.
> > - For each SoC's PMU support now we can add platform data and statically
> > bind PMU configuration and SoC specific initialization function.
> > - Separate each SoC's PMU initialization function and make it as part of
> > platform data.
> > - It also removes uses of soc_is_exynosXYZ().
> >
> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> > Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> > ---
> > arch/arm/mach-exynos/Kconfig | 1 +
> > arch/arm/mach-exynos/pmu.c | 185
> +++++++++++++++++++++++++++++++++---------
> > 2 files changed, 146 insertions(+), 40 deletions(-)
> >
> Looks good to me, will apply this and 4/4.
>
We need to hold these two patches until dependent patch [1] from Tomasz Figa
gets merged.
[1]: mfd: syscon: Decouple syscon interface from syscon devices
https://lkml.org/lkml/2014/6/24/188
Thanks,
Pankaj Dubey
> Thanks,
> Kukjin
>
> > diff --git a/arch/arm/mach-exynos/Kconfig
> > b/arch/arm/mach-exynos/Kconfig index 8f9b66c..a2944ac 100644
> > --- a/arch/arm/mach-exynos/Kconfig
> > +++ b/arch/arm/mach-exynos/Kconfig
> > @@ -24,6 +24,7 @@ menuconfig ARCH_EXYNOS
> > select PM_GENERIC_DOMAINS if PM_RUNTIME
> > select S5P_DEV_MFC
> > select SRAM
> > + select MFD_SYSCON
> > help
> > Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
> >
> > diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
> > index ff9d23f..5b76728 100644
> > --- a/arch/arm/mach-exynos/pmu.c
> > +++ b/arch/arm/mach-exynos/pmu.c
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
> > + * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
> > * http://www.samsung.com/
> > *
> > * EXYNOS - CPU PMU(Power Management Unit) support @@ -10,12 +10,28
> > @@
> > */
> >
> > #include <linux/io.h>
> > -#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +#include <linux/mfd/syscon.h>
> >
> > #include "common.h"
> > #include "regs-pmu.h"
> >
> > -static const struct exynos_pmu_conf *exynos_pmu_config;
> > +struct exynos_pmu_data {
> > + const struct exynos_pmu_conf *pmu_config;
> > + const struct exynos_pmu_conf *pmu_config_extra;
> > +
> > + void (*pmu_init)(void);
> > + void (*powerdown_conf)(enum sys_powerdown); };
> > +
> > +struct exynos_pmu_context {
> > + struct device *dev;
> > + const struct exynos_pmu_data *pmu_data; };
> > +
> > +static struct exynos_pmu_context *pmu_context;
> >
> > static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
> > /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ @@ -335,7
> > +351,7 @@ static unsigned int const exynos5_list_diable_wfi_wfe[] = {
> > EXYNOS5_ISP_ARM_OPTION,
> > };
> >
> > -static void exynos5_init_pmu(void)
> > +static void exynos5_powerdown_conf(enum sys_powerdown mode)
> > {
> > unsigned int i;
> > unsigned int tmp;
> > @@ -372,51 +388,140 @@ void exynos_sys_powerdown_conf(enum
> > sys_powerdown mode) {
> > unsigned int i;
> >
> > - if (soc_is_exynos5250())
> > - exynos5_init_pmu();
> > + const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
> >
> > - for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
> > - pmu_raw_writel(exynos_pmu_config[i].val[mode],
> > - exynos_pmu_config[i].offset);
> > + if (pmu_data->powerdown_conf)
> > + pmu_data->powerdown_conf(mode);
> >
> > - if (soc_is_exynos4412()) {
> > - for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END
;
> i++)
> > - pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
> > - exynos4412_pmu_config[i].offset);
> > + if (pmu_data->pmu_config) {
> > + for (i = 0; (pmu_data->pmu_config[i].offset !=
PMU_TABLE_END)
> ; i++)
> > + pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
> > + pmu_data->pmu_config[i].offset);
> > + }
> > +
> > + if (pmu_data->pmu_config_extra) {
> > + for (i = 0; pmu_data->pmu_config_extra[i].offset !=
> PMU_TABLE_END; i++)
> > +
pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
> > +
pmu_data->pmu_config_extra[i].offset);
> > }
> > }
> >
> > -static int __init exynos_pmu_init(void)
> > +static void exynos5250_pmu_init(void)
> > {
> > unsigned int value;
> > + /*
> > + * When SYS_WDTRESET is set, watchdog timer reset request
> > + * is ignored by power management unit.
> > + */
> > + value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> > + value &= ~EXYNOS5_SYS_WDTRESET;
> > + pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
> > +
> > + value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> > + value &= ~EXYNOS5_SYS_WDTRESET;
> > + pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); }
> > +
> > +static const struct exynos_pmu_data exynos4210_pmu_data = {
> > + .pmu_config = exynos4210_pmu_config,
> > +};
> > +
> > +static const struct exynos_pmu_data exynos4212_pmu_data = {
> > + .pmu_config = exynos4x12_pmu_config,
> > +};
> > +
> > +static const struct exynos_pmu_data exynos4412_pmu_data = {
> > + .pmu_config = exynos4x12_pmu_config,
> > + .pmu_config_extra = exynos4412_pmu_config,
> > +};
> > +
> > +static const struct exynos_pmu_data exynos5250_pmu_data = {
> > + .pmu_config = exynos5250_pmu_config,
> > + .pmu_init = exynos5250_pmu_init,
> > + .powerdown_conf = exynos5_powerdown_conf,
> > +};
> > +
> > +static const struct regmap_config pmu_regmap_config = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > +};
> >
> > - exynos_pmu_config = exynos4210_pmu_config;
> > -
> > - if (soc_is_exynos4210()) {
> > - exynos_pmu_config = exynos4210_pmu_config;
> > - pr_info("EXYNOS4210 PMU Initialize\n");
> > - } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
> > - exynos_pmu_config = exynos4x12_pmu_config;
> > - pr_info("EXYNOS4x12 PMU Initialize\n");
> > - } else if (soc_is_exynos5250()) {
> > - /*
> > - * When SYS_WDTRESET is set, watchdog timer reset request
> > - * is ignored by power management unit.
> > - */
> > - value =
> pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> > - value &= ~EXYNOS5_SYS_WDTRESET;
> > - pmu_raw_writel(value,
> EXYNOS5_AUTO_WDTRESET_DISABLE);
> > -
> > - value =
> pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> > - value &= ~EXYNOS5_SYS_WDTRESET;
> > - pmu_raw_writel(value,
> EXYNOS5_MASK_WDTRESET_REQUEST);
> > -
> > - exynos_pmu_config = exynos5250_pmu_config;
> > - pr_info("EXYNOS5250 PMU Initialize\n");
> > - } else {
> > - pr_info("EXYNOS: PMU not supported\n");
> > +/*
> > + * PMU platform driver and devicetree bindings.
> > + */
> > +static const struct of_device_id exynos_pmu_of_device_ids[] = {
> > + {
> > + .compatible = "samsung,exynos4210-pmu",
> > + .data = &exynos4210_pmu_data,
> > + }, {
> > + .compatible = "samsung,exynos4212-pmu",
> > + .data = &exynos4212_pmu_data,
> > + }, {
> > + .compatible = "samsung,exynos4412-pmu",
> > + .data = &exynos4412_pmu_data,
> > + }, {
> > + .compatible = "samsung,exynos5250-pmu",
> > + .data = &exynos5250_pmu_data,
> > + },
> > + { /*sentinel*/ },
> > +};
> > +
> > +static int exynos_pmu_probe(struct platform_device *pdev) {
> > + const struct of_device_id *match;
> > + struct device *dev = &pdev->dev;
> > + struct regmap *regmap;
> > + struct resource *res;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + pmu_base_addr = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(pmu_base_addr))
> > + return PTR_ERR(pmu_base_addr);
> > +
> > + pmu_context = devm_kzalloc(&pdev->dev,
> > + sizeof(struct exynos_pmu_context),
> > + GFP_KERNEL);
> > + if (!pmu_context) {
> > + dev_err(dev, "Cannot allocate memory.\n");
> > + return -ENOMEM;
> > + }
> > + pmu_context->dev = dev;
> > +
> > + regmap = devm_regmap_init_mmio(dev, pmu_base_addr,
> > + &pmu_regmap_config);
> > + if (IS_ERR(regmap)) {
> > + dev_err(dev, "regmap init failed\n");
> > + return PTR_ERR(regmap);
> > }
> >
> > + devm_syscon_register(dev, regmap);
> > +
> > + match = of_match_node(exynos_pmu_of_device_ids, pdev->dev.of_node);
> > +
> > + pmu_context->pmu_data = match->data;
> > +
> > + if (pmu_context->pmu_data->pmu_init)
> > + pmu_context->pmu_data->pmu_init();
> > +
> > + platform_set_drvdata(pdev, pmu_context);
> > +
> > + dev_dbg(dev, "Exynos PMU Driver probe done\n");
> > return 0;
> > }
> > -arch_initcall(exynos_pmu_init);
> > +
> > +static struct platform_driver exynos_pmu_driver = {
> > + .driver = {
> > + .name = "exynos-pmu",
> > + .owner = THIS_MODULE,
> > + .of_match_table = exynos_pmu_of_device_ids,
> > + },
> > + .probe = exynos_pmu_probe,
> > +};
> > +
> > +static int __init exynos_pmu_init(void) {
> > + return platform_driver_register(&exynos_pmu_driver);
> > +
> > +}
> > +postcore_initcall(exynos_pmu_init);
> > --
> > 1.7.9.5
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
@ 2014-07-25 5:32 ` Pankaj Dubey
0 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-25 5:32 UTC (permalink / raw)
To: linux-arm-kernel
Hi Kukjin,
On Friday, July 25, 2014 Kukjin Kim wrote:
> Subject: RE: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for
> Exynos PMU
>
> Pankaj Dubey wrote:
> >
> > This patch modifies Exynos Power Management Unit (PMU) initialization
> > implementation in following way:
> >
> > - Added platform driver support and probe function where Exynos PMU
> > driver will register itself as syscon provider with syscon framework.
> > - Added platform struct exynos_pmu_data to hold platform specific data.
> > - For each SoC's PMU support now we can add platform data and statically
> > bind PMU configuration and SoC specific initialization function.
> > - Separate each SoC's PMU initialization function and make it as part of
> > platform data.
> > - It also removes uses of soc_is_exynosXYZ().
> >
> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> > Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> > ---
> > arch/arm/mach-exynos/Kconfig | 1 +
> > arch/arm/mach-exynos/pmu.c | 185
> +++++++++++++++++++++++++++++++++---------
> > 2 files changed, 146 insertions(+), 40 deletions(-)
> >
> Looks good to me, will apply this and 4/4.
>
We need to hold these two patches until dependent patch [1] from Tomasz Figa
gets merged.
[1]: mfd: syscon: Decouple syscon interface from syscon devices
https://lkml.org/lkml/2014/6/24/188
Thanks,
Pankaj Dubey
> Thanks,
> Kukjin
>
> > diff --git a/arch/arm/mach-exynos/Kconfig
> > b/arch/arm/mach-exynos/Kconfig index 8f9b66c..a2944ac 100644
> > --- a/arch/arm/mach-exynos/Kconfig
> > +++ b/arch/arm/mach-exynos/Kconfig
> > @@ -24,6 +24,7 @@ menuconfig ARCH_EXYNOS
> > select PM_GENERIC_DOMAINS if PM_RUNTIME
> > select S5P_DEV_MFC
> > select SRAM
> > + select MFD_SYSCON
> > help
> > Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
> >
> > diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
> > index ff9d23f..5b76728 100644
> > --- a/arch/arm/mach-exynos/pmu.c
> > +++ b/arch/arm/mach-exynos/pmu.c
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
> > + * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
> > * http://www.samsung.com/
> > *
> > * EXYNOS - CPU PMU(Power Management Unit) support @@ -10,12 +10,28
> > @@
> > */
> >
> > #include <linux/io.h>
> > -#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +#include <linux/mfd/syscon.h>
> >
> > #include "common.h"
> > #include "regs-pmu.h"
> >
> > -static const struct exynos_pmu_conf *exynos_pmu_config;
> > +struct exynos_pmu_data {
> > + const struct exynos_pmu_conf *pmu_config;
> > + const struct exynos_pmu_conf *pmu_config_extra;
> > +
> > + void (*pmu_init)(void);
> > + void (*powerdown_conf)(enum sys_powerdown); };
> > +
> > +struct exynos_pmu_context {
> > + struct device *dev;
> > + const struct exynos_pmu_data *pmu_data; };
> > +
> > +static struct exynos_pmu_context *pmu_context;
> >
> > static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
> > /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ @@ -335,7
> > +351,7 @@ static unsigned int const exynos5_list_diable_wfi_wfe[] = {
> > EXYNOS5_ISP_ARM_OPTION,
> > };
> >
> > -static void exynos5_init_pmu(void)
> > +static void exynos5_powerdown_conf(enum sys_powerdown mode)
> > {
> > unsigned int i;
> > unsigned int tmp;
> > @@ -372,51 +388,140 @@ void exynos_sys_powerdown_conf(enum
> > sys_powerdown mode) {
> > unsigned int i;
> >
> > - if (soc_is_exynos5250())
> > - exynos5_init_pmu();
> > + const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
> >
> > - for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
> > - pmu_raw_writel(exynos_pmu_config[i].val[mode],
> > - exynos_pmu_config[i].offset);
> > + if (pmu_data->powerdown_conf)
> > + pmu_data->powerdown_conf(mode);
> >
> > - if (soc_is_exynos4412()) {
> > - for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END
;
> i++)
> > - pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
> > - exynos4412_pmu_config[i].offset);
> > + if (pmu_data->pmu_config) {
> > + for (i = 0; (pmu_data->pmu_config[i].offset !=
PMU_TABLE_END)
> ; i++)
> > + pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
> > + pmu_data->pmu_config[i].offset);
> > + }
> > +
> > + if (pmu_data->pmu_config_extra) {
> > + for (i = 0; pmu_data->pmu_config_extra[i].offset !=
> PMU_TABLE_END; i++)
> > +
pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
> > +
pmu_data->pmu_config_extra[i].offset);
> > }
> > }
> >
> > -static int __init exynos_pmu_init(void)
> > +static void exynos5250_pmu_init(void)
> > {
> > unsigned int value;
> > + /*
> > + * When SYS_WDTRESET is set, watchdog timer reset request
> > + * is ignored by power management unit.
> > + */
> > + value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> > + value &= ~EXYNOS5_SYS_WDTRESET;
> > + pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
> > +
> > + value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> > + value &= ~EXYNOS5_SYS_WDTRESET;
> > + pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); }
> > +
> > +static const struct exynos_pmu_data exynos4210_pmu_data = {
> > + .pmu_config = exynos4210_pmu_config,
> > +};
> > +
> > +static const struct exynos_pmu_data exynos4212_pmu_data = {
> > + .pmu_config = exynos4x12_pmu_config,
> > +};
> > +
> > +static const struct exynos_pmu_data exynos4412_pmu_data = {
> > + .pmu_config = exynos4x12_pmu_config,
> > + .pmu_config_extra = exynos4412_pmu_config,
> > +};
> > +
> > +static const struct exynos_pmu_data exynos5250_pmu_data = {
> > + .pmu_config = exynos5250_pmu_config,
> > + .pmu_init = exynos5250_pmu_init,
> > + .powerdown_conf = exynos5_powerdown_conf,
> > +};
> > +
> > +static const struct regmap_config pmu_regmap_config = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > +};
> >
> > - exynos_pmu_config = exynos4210_pmu_config;
> > -
> > - if (soc_is_exynos4210()) {
> > - exynos_pmu_config = exynos4210_pmu_config;
> > - pr_info("EXYNOS4210 PMU Initialize\n");
> > - } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
> > - exynos_pmu_config = exynos4x12_pmu_config;
> > - pr_info("EXYNOS4x12 PMU Initialize\n");
> > - } else if (soc_is_exynos5250()) {
> > - /*
> > - * When SYS_WDTRESET is set, watchdog timer reset request
> > - * is ignored by power management unit.
> > - */
> > - value =
> pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
> > - value &= ~EXYNOS5_SYS_WDTRESET;
> > - pmu_raw_writel(value,
> EXYNOS5_AUTO_WDTRESET_DISABLE);
> > -
> > - value =
> pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
> > - value &= ~EXYNOS5_SYS_WDTRESET;
> > - pmu_raw_writel(value,
> EXYNOS5_MASK_WDTRESET_REQUEST);
> > -
> > - exynos_pmu_config = exynos5250_pmu_config;
> > - pr_info("EXYNOS5250 PMU Initialize\n");
> > - } else {
> > - pr_info("EXYNOS: PMU not supported\n");
> > +/*
> > + * PMU platform driver and devicetree bindings.
> > + */
> > +static const struct of_device_id exynos_pmu_of_device_ids[] = {
> > + {
> > + .compatible = "samsung,exynos4210-pmu",
> > + .data = &exynos4210_pmu_data,
> > + }, {
> > + .compatible = "samsung,exynos4212-pmu",
> > + .data = &exynos4212_pmu_data,
> > + }, {
> > + .compatible = "samsung,exynos4412-pmu",
> > + .data = &exynos4412_pmu_data,
> > + }, {
> > + .compatible = "samsung,exynos5250-pmu",
> > + .data = &exynos5250_pmu_data,
> > + },
> > + { /*sentinel*/ },
> > +};
> > +
> > +static int exynos_pmu_probe(struct platform_device *pdev) {
> > + const struct of_device_id *match;
> > + struct device *dev = &pdev->dev;
> > + struct regmap *regmap;
> > + struct resource *res;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + pmu_base_addr = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(pmu_base_addr))
> > + return PTR_ERR(pmu_base_addr);
> > +
> > + pmu_context = devm_kzalloc(&pdev->dev,
> > + sizeof(struct exynos_pmu_context),
> > + GFP_KERNEL);
> > + if (!pmu_context) {
> > + dev_err(dev, "Cannot allocate memory.\n");
> > + return -ENOMEM;
> > + }
> > + pmu_context->dev = dev;
> > +
> > + regmap = devm_regmap_init_mmio(dev, pmu_base_addr,
> > + &pmu_regmap_config);
> > + if (IS_ERR(regmap)) {
> > + dev_err(dev, "regmap init failed\n");
> > + return PTR_ERR(regmap);
> > }
> >
> > + devm_syscon_register(dev, regmap);
> > +
> > + match = of_match_node(exynos_pmu_of_device_ids, pdev->dev.of_node);
> > +
> > + pmu_context->pmu_data = match->data;
> > +
> > + if (pmu_context->pmu_data->pmu_init)
> > + pmu_context->pmu_data->pmu_init();
> > +
> > + platform_set_drvdata(pdev, pmu_context);
> > +
> > + dev_dbg(dev, "Exynos PMU Driver probe done\n");
> > return 0;
> > }
> > -arch_initcall(exynos_pmu_init);
> > +
> > +static struct platform_driver exynos_pmu_driver = {
> > + .driver = {
> > + .name = "exynos-pmu",
> > + .owner = THIS_MODULE,
> > + .of_match_table = exynos_pmu_of_device_ids,
> > + },
> > + .probe = exynos_pmu_probe,
> > +};
> > +
> > +static int __init exynos_pmu_init(void) {
> > + return platform_driver_register(&exynos_pmu_driver);
> > +
> > +}
> > +postcore_initcall(exynos_pmu_init);
> > --
> > 1.7.9.5
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
2014-07-25 5:32 ` Pankaj Dubey
@ 2014-07-25 11:00 ` Tomasz Figa
-1 siblings, 0 replies; 35+ messages in thread
From: Tomasz Figa @ 2014-07-25 11:00 UTC (permalink / raw)
To: Pankaj Dubey, 'Kukjin Kim',
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: linux, t.figa, vikas.sajjan, joshi, naushad, thomas.ab, chow.kim
Hi Pankaj, Kukjin,
On 25.07.2014 07:32, Pankaj Dubey wrote:
> Hi Kukjin,
>
> On Friday, July 25, 2014 Kukjin Kim wrote:
[snip]
>>>
>> Looks good to me, will apply this and 4/4.
>>
>
> We need to hold these two patches until dependent patch [1] from Tomasz Figa
> gets merged.
>
> [1]: mfd: syscon: Decouple syscon interface from syscon devices
> https://lkml.org/lkml/2014/6/24/188
That RFC patch had few comments from Arnd needed to be addressed, so it
needs a new revision.
Pankaj, If I remember correctly, we had talked about this and the
conclusion was that you would take care of addressing the comments and
sending new version of the patch. Any update on this or have I missed
something?
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
@ 2014-07-25 11:00 ` Tomasz Figa
0 siblings, 0 replies; 35+ messages in thread
From: Tomasz Figa @ 2014-07-25 11:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi Pankaj, Kukjin,
On 25.07.2014 07:32, Pankaj Dubey wrote:
> Hi Kukjin,
>
> On Friday, July 25, 2014 Kukjin Kim wrote:
[snip]
>>>
>> Looks good to me, will apply this and 4/4.
>>
>
> We need to hold these two patches until dependent patch [1] from Tomasz Figa
> gets merged.
>
> [1]: mfd: syscon: Decouple syscon interface from syscon devices
> https://lkml.org/lkml/2014/6/24/188
That RFC patch had few comments from Arnd needed to be addressed, so it
needs a new revision.
Pankaj, If I remember correctly, we had talked about this and the
conclusion was that you would take care of addressing the comments and
sending new version of the patch. Any update on this or have I missed
something?
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v7 1/4] ARM: EXYNOS: Add support for mapping PMU base address via DT
2014-07-10 13:49 ` Kukjin Kim
@ 2014-07-27 3:33 ` Andreas Färber
-1 siblings, 0 replies; 35+ messages in thread
From: Andreas Färber @ 2014-07-27 3:33 UTC (permalink / raw)
To: Kukjin Kim, 'Pankaj Dubey',
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: linux, t.figa, vikas.sajjan, joshi, naushad, thomas.ab, chow.kim
Am 10.07.2014 15:49, schrieb Kukjin Kim:
> Pankaj Dubey wrote:
>>
>> Add support for mapping Samsung Power Management Unit (PMU)
>> base address from device tree.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
>> ---
>> arch/arm/mach-exynos/common.h | 1 +
>> arch/arm/mach-exynos/exynos.c | 37 +++++++++++++++++++++++++++++++++++++
>> 2 files changed, 38 insertions(+)
>>
>> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
>> index 152b464..f8daa9c 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
>>
>> extern void __iomem *sysram_ns_base_addr;
>> extern void __iomem *sysram_base_addr;
>> +extern void __iomem *pmu_base_addr;
>> void exynos_sysram_init(void);
>>
>> void exynos_firmware_init(void);
>> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
>> index 186f35d..173aac8 100644
>> --- a/arch/arm/mach-exynos/exynos.c
>> +++ b/arch/arm/mach-exynos/exynos.c
>> @@ -19,6 +19,7 @@
>> #include <linux/of_platform.h>
>> #include <linux/platform_device.h>
>> #include <linux/pm_domain.h>
>> +#include <linux/irqchip.h>
>>
>> #include <asm/cacheflush.h>
>> #include <asm/hardware/cache-l2x0.h>
>> @@ -31,6 +32,8 @@
>> #include "regs-pmu.h"
>> #include "regs-sys.h"
>>
>> +void __iomem *pmu_base_addr;
>> +
>> static struct map_desc exynos4_iodesc[] __initdata = {
>> {
>> .virtual = (unsigned long)S3C_VA_SYS,
>> @@ -253,6 +256,39 @@ static void __init exynos_init_io(void)
>> exynos_map_io();
>> }
>>
>> +static const struct of_device_id exynos_dt_pmu_match[] = {
>> + { .compatible = "samsung,exynos3250-pmu" },
>> + { .compatible = "samsung,exynos4210-pmu" },
>> + { .compatible = "samsung,exynos4212-pmu" },
>> + { .compatible = "samsung,exynos4412-pmu" },
>> + { .compatible = "samsung,exynos5250-pmu" },
>> + { .compatible = "samsung,exynos5420-pmu" },
>> + { /*sentinel*/ },
>> +};
>> +
>> +static void exynos_map_pmu(void)
>> +{
>> + struct device_node *np;
>> +
>> + np = of_find_matching_node(NULL, exynos_dt_pmu_match);
>> + if (np)
>> + pmu_base_addr = of_iomap(np, 0);
>> +
>> + if (!pmu_base_addr)
>> + panic("failed to find exynos pmu register\n");
>> +}
>> +
>> +static void __init exynos_init_irq(void)
>> +{
>> + irqchip_init();
>> + /*
>> + * Since platsmp.c needs pmu base address by the time
>> + * DT is not unflatten so we can't use DT APIs before
Either "Since platsmp.c needs ... unflattened, we can't ..."
or "platsmp.c needs ... unflattened, so we can't ..."
>> + * init_irq
>> + */
>> + exynos_map_pmu();
>> +}
>> +
>> static void __init exynos_dt_machine_init(void)
>> {
>> struct device_node *i2c_np;
>> @@ -336,6 +372,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
>> .smp = smp_ops(exynos_smp_ops),
>> .map_io = exynos_init_io,
>> .init_early = exynos_firmware_init,
>> + .init_irq = exynos_init_irq,
>> .init_machine = exynos_dt_machine_init,
>> .init_late = exynos_init_late,
>> .dt_compat = exynos_dt_compat,
>> --
>> 1.7.9.5
>
> Looks good to me, will apply.
Unfortunately this broke the boot on ODROID-XU: Neither is there a
exynos_dt_pmu_match[] entry for 5410 nor is such a node defined in
exynos5410.dtsi. Not having access to a TRM, should 5410 get a node like
5420? Might SoCs beyond 5420 also require changes?
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 1/4] ARM: EXYNOS: Add support for mapping PMU base address via DT
@ 2014-07-27 3:33 ` Andreas Färber
0 siblings, 0 replies; 35+ messages in thread
From: Andreas Färber @ 2014-07-27 3:33 UTC (permalink / raw)
To: linux-arm-kernel
Am 10.07.2014 15:49, schrieb Kukjin Kim:
> Pankaj Dubey wrote:
>>
>> Add support for mapping Samsung Power Management Unit (PMU)
>> base address from device tree.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
>> ---
>> arch/arm/mach-exynos/common.h | 1 +
>> arch/arm/mach-exynos/exynos.c | 37 +++++++++++++++++++++++++++++++++++++
>> 2 files changed, 38 insertions(+)
>>
>> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
>> index 152b464..f8daa9c 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
>>
>> extern void __iomem *sysram_ns_base_addr;
>> extern void __iomem *sysram_base_addr;
>> +extern void __iomem *pmu_base_addr;
>> void exynos_sysram_init(void);
>>
>> void exynos_firmware_init(void);
>> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
>> index 186f35d..173aac8 100644
>> --- a/arch/arm/mach-exynos/exynos.c
>> +++ b/arch/arm/mach-exynos/exynos.c
>> @@ -19,6 +19,7 @@
>> #include <linux/of_platform.h>
>> #include <linux/platform_device.h>
>> #include <linux/pm_domain.h>
>> +#include <linux/irqchip.h>
>>
>> #include <asm/cacheflush.h>
>> #include <asm/hardware/cache-l2x0.h>
>> @@ -31,6 +32,8 @@
>> #include "regs-pmu.h"
>> #include "regs-sys.h"
>>
>> +void __iomem *pmu_base_addr;
>> +
>> static struct map_desc exynos4_iodesc[] __initdata = {
>> {
>> .virtual = (unsigned long)S3C_VA_SYS,
>> @@ -253,6 +256,39 @@ static void __init exynos_init_io(void)
>> exynos_map_io();
>> }
>>
>> +static const struct of_device_id exynos_dt_pmu_match[] = {
>> + { .compatible = "samsung,exynos3250-pmu" },
>> + { .compatible = "samsung,exynos4210-pmu" },
>> + { .compatible = "samsung,exynos4212-pmu" },
>> + { .compatible = "samsung,exynos4412-pmu" },
>> + { .compatible = "samsung,exynos5250-pmu" },
>> + { .compatible = "samsung,exynos5420-pmu" },
>> + { /*sentinel*/ },
>> +};
>> +
>> +static void exynos_map_pmu(void)
>> +{
>> + struct device_node *np;
>> +
>> + np = of_find_matching_node(NULL, exynos_dt_pmu_match);
>> + if (np)
>> + pmu_base_addr = of_iomap(np, 0);
>> +
>> + if (!pmu_base_addr)
>> + panic("failed to find exynos pmu register\n");
>> +}
>> +
>> +static void __init exynos_init_irq(void)
>> +{
>> + irqchip_init();
>> + /*
>> + * Since platsmp.c needs pmu base address by the time
>> + * DT is not unflatten so we can't use DT APIs before
Either "Since platsmp.c needs ... unflattened, we can't ..."
or "platsmp.c needs ... unflattened, so we can't ..."
>> + * init_irq
>> + */
>> + exynos_map_pmu();
>> +}
>> +
>> static void __init exynos_dt_machine_init(void)
>> {
>> struct device_node *i2c_np;
>> @@ -336,6 +372,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
>> .smp = smp_ops(exynos_smp_ops),
>> .map_io = exynos_init_io,
>> .init_early = exynos_firmware_init,
>> + .init_irq = exynos_init_irq,
>> .init_machine = exynos_dt_machine_init,
>> .init_late = exynos_init_late,
>> .dt_compat = exynos_dt_compat,
>> --
>> 1.7.9.5
>
> Looks good to me, will apply.
Unfortunately this broke the boot on ODROID-XU: Neither is there a
exynos_dt_pmu_match[] entry for 5410 nor is such a node defined in
exynos5410.dtsi. Not having access to a TRM, should 5410 get a node like
5420? Might SoCs beyond 5420 also require changes?
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
2014-07-25 11:00 ` Tomasz Figa
@ 2014-07-28 3:10 ` Pankaj Dubey
-1 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-28 3:10 UTC (permalink / raw)
To: 'Tomasz Figa', 'Kukjin Kim',
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: linux, t.figa, vikas.sajjan, joshi, naushad, thomas.ab, chow.kim
Hi Tomasz,
On Friday, July 25, 2014 Tomasz Figa wrote:
> To: Pankaj Dubey; 'Kukjin Kim'; linux-arm-kernel@lists.infradead.org;
linux-
> samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: linux@arm.linux.org.uk; t.figa@samsung.com; vikas.sajjan@samsung.com;
> joshi@samsung.com; naushad@samsung.com; thomas.ab@samsung.com;
> chow.kim@samsung.com
> Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for
> Exynos PMU
>
> Hi Pankaj, Kukjin,
>
> On 25.07.2014 07:32, Pankaj Dubey wrote:
> > Hi Kukjin,
> >
> > On Friday, July 25, 2014 Kukjin Kim wrote:
>
> [snip]
>
> >>>
> >> Looks good to me, will apply this and 4/4.
> >>
> >
> > We need to hold these two patches until dependent patch [1] from
> > Tomasz Figa gets merged.
> >
> > [1]: mfd: syscon: Decouple syscon interface from syscon devices
> > https://lkml.org/lkml/2014/6/24/188
>
> That RFC patch had few comments from Arnd needed to be addressed, so it
needs a
> new revision.
>
> Pankaj, If I remember correctly, we had talked about this and the
conclusion was that
> you would take care of addressing the comments and sending new version of
the
> patch. Any update on this or have I missed something?
>
Well, I don't think we concluded as such anything.
Since this patch needs to get in so that Exynos PMU and PM related changes
can go in,
I discussed with you saying that I am not able to understand about Arnd's
comments and
if possible and time permits I will look into it. Meanwhile I got busy with
some other
official work, so could not get time to look into it.
> Best regards,
> Tomasz
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
@ 2014-07-28 3:10 ` Pankaj Dubey
0 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-07-28 3:10 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tomasz,
On Friday, July 25, 2014 Tomasz Figa wrote:
> To: Pankaj Dubey; 'Kukjin Kim'; linux-arm-kernel at lists.infradead.org;
linux-
> samsung-soc at vger.kernel.org; linux-kernel at vger.kernel.org
> Cc: linux at arm.linux.org.uk; t.figa at samsung.com; vikas.sajjan at samsung.com;
> joshi at samsung.com; naushad at samsung.com; thomas.ab at samsung.com;
> chow.kim at samsung.com
> Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for
> Exynos PMU
>
> Hi Pankaj, Kukjin,
>
> On 25.07.2014 07:32, Pankaj Dubey wrote:
> > Hi Kukjin,
> >
> > On Friday, July 25, 2014 Kukjin Kim wrote:
>
> [snip]
>
> >>>
> >> Looks good to me, will apply this and 4/4.
> >>
> >
> > We need to hold these two patches until dependent patch [1] from
> > Tomasz Figa gets merged.
> >
> > [1]: mfd: syscon: Decouple syscon interface from syscon devices
> > https://lkml.org/lkml/2014/6/24/188
>
> That RFC patch had few comments from Arnd needed to be addressed, so it
needs a
> new revision.
>
> Pankaj, If I remember correctly, we had talked about this and the
conclusion was that
> you would take care of addressing the comments and sending new version of
the
> patch. Any update on this or have I missed something?
>
Well, I don't think we concluded as such anything.
Since this patch needs to get in so that Exynos PMU and PM related changes
can go in,
I discussed with you saying that I am not able to understand about Arnd's
comments and
if possible and time permits I will look into it. Meanwhile I got busy with
some other
official work, so could not get time to look into it.
> Best regards,
> Tomasz
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
2014-07-28 3:10 ` Pankaj Dubey
@ 2014-08-18 17:42 ` Bartlomiej Zolnierkiewicz
-1 siblings, 0 replies; 35+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2014-08-18 17:42 UTC (permalink / raw)
To: Pankaj Dubey, 'Tomasz Figa', 'Kukjin Kim'
Cc: linux-arm-kernel, linux-samsung-soc, linux-kernel, linux, t.figa,
vikas.sajjan, joshi, naushad, thomas.ab, chow.kim
Hi,
On Monday, July 28, 2014 08:40:52 AM Pankaj Dubey wrote:
> Hi Tomasz,
>
> On Friday, July 25, 2014 Tomasz Figa wrote:
>
> > To: Pankaj Dubey; 'Kukjin Kim'; linux-arm-kernel@lists.infradead.org;
> linux-
> > samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org
> > Cc: linux@arm.linux.org.uk; t.figa@samsung.com; vikas.sajjan@samsung.com;
> > joshi@samsung.com; naushad@samsung.com; thomas.ab@samsung.com;
> > chow.kim@samsung.com
> > Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for
> > Exynos PMU
> >
> > Hi Pankaj, Kukjin,
> >
> > On 25.07.2014 07:32, Pankaj Dubey wrote:
> > > Hi Kukjin,
> > >
> > > On Friday, July 25, 2014 Kukjin Kim wrote:
> >
> > [snip]
> >
> > >>>
> > >> Looks good to me, will apply this and 4/4.
> > >>
> > >
> > > We need to hold these two patches until dependent patch [1] from
> > > Tomasz Figa gets merged.
> > >
> > > [1]: mfd: syscon: Decouple syscon interface from syscon devices
> > > https://lkml.org/lkml/2014/6/24/188
> >
> > That RFC patch had few comments from Arnd needed to be addressed, so it
> needs a
> > new revision.
> >
> > Pankaj, If I remember correctly, we had talked about this and the
> conclusion was that
> > you would take care of addressing the comments and sending new version of
> the
> > patch. Any update on this or have I missed something?
> >
>
> Well, I don't think we concluded as such anything.
> Since this patch needs to get in so that Exynos PMU and PM related changes
> can go in,
> I discussed with you saying that I am not able to understand about Arnd's
> comments and
> if possible and time permits I will look into it. Meanwhile I got busy with
> some other
> official work, so could not get time to look into it.
Tomasz/Pankaj, could we please get some agreement on what needs to be
done and who should do the pending work?
syscon patch is blocking PMU cleanup patches which in turn are blocking
PMU support additions for new SoCs (Exynos5420/5800 and Exynos3250 PMU
patches).
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
@ 2014-08-18 17:42 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 35+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2014-08-18 17:42 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Monday, July 28, 2014 08:40:52 AM Pankaj Dubey wrote:
> Hi Tomasz,
>
> On Friday, July 25, 2014 Tomasz Figa wrote:
>
> > To: Pankaj Dubey; 'Kukjin Kim'; linux-arm-kernel at lists.infradead.org;
> linux-
> > samsung-soc at vger.kernel.org; linux-kernel at vger.kernel.org
> > Cc: linux at arm.linux.org.uk; t.figa at samsung.com; vikas.sajjan at samsung.com;
> > joshi at samsung.com; naushad at samsung.com; thomas.ab at samsung.com;
> > chow.kim at samsung.com
> > Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for
> > Exynos PMU
> >
> > Hi Pankaj, Kukjin,
> >
> > On 25.07.2014 07:32, Pankaj Dubey wrote:
> > > Hi Kukjin,
> > >
> > > On Friday, July 25, 2014 Kukjin Kim wrote:
> >
> > [snip]
> >
> > >>>
> > >> Looks good to me, will apply this and 4/4.
> > >>
> > >
> > > We need to hold these two patches until dependent patch [1] from
> > > Tomasz Figa gets merged.
> > >
> > > [1]: mfd: syscon: Decouple syscon interface from syscon devices
> > > https://lkml.org/lkml/2014/6/24/188
> >
> > That RFC patch had few comments from Arnd needed to be addressed, so it
> needs a
> > new revision.
> >
> > Pankaj, If I remember correctly, we had talked about this and the
> conclusion was that
> > you would take care of addressing the comments and sending new version of
> the
> > patch. Any update on this or have I missed something?
> >
>
> Well, I don't think we concluded as such anything.
> Since this patch needs to get in so that Exynos PMU and PM related changes
> can go in,
> I discussed with you saying that I am not able to understand about Arnd's
> comments and
> if possible and time permits I will look into it. Meanwhile I got busy with
> some other
> official work, so could not get time to look into it.
Tomasz/Pankaj, could we please get some agreement on what needs to be
done and who should do the pending work?
syscon patch is blocking PMU cleanup patches which in turn are blocking
PMU support additions for new SoCs (Exynos5420/5800 and Exynos3250 PMU
patches).
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
2014-08-18 17:42 ` Bartlomiej Zolnierkiewicz
@ 2014-08-19 14:30 ` Tomasz Figa
-1 siblings, 0 replies; 35+ messages in thread
From: Tomasz Figa @ 2014-08-19 14:30 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz, Pankaj Dubey, 'Kukjin Kim'
Cc: linux-arm-kernel, linux-samsung-soc, linux-kernel, linux, t.figa,
vikas.sajjan, joshi, naushad, thomas.ab, chow.kim
Hi Bart,
On 18.08.2014 19:42, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> On Monday, July 28, 2014 08:40:52 AM Pankaj Dubey wrote:
>> Hi Tomasz,
>>
>> On Friday, July 25, 2014 Tomasz Figa wrote:
>>
>>> To: Pankaj Dubey; 'Kukjin Kim'; linux-arm-kernel@lists.infradead.org;
>> linux-
>>> samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org
>>> Cc: linux@arm.linux.org.uk; t.figa@samsung.com; vikas.sajjan@samsung.com;
>>> joshi@samsung.com; naushad@samsung.com; thomas.ab@samsung.com;
>>> chow.kim@samsung.com
>>> Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for
>>> Exynos PMU
>>>
>>> Hi Pankaj, Kukjin,
>>>
>>> On 25.07.2014 07:32, Pankaj Dubey wrote:
>>>> Hi Kukjin,
>>>>
>>>> On Friday, July 25, 2014 Kukjin Kim wrote:
>>>
>>> [snip]
>>>
>>>>>>
>>>>> Looks good to me, will apply this and 4/4.
>>>>>
>>>>
>>>> We need to hold these two patches until dependent patch [1] from
>>>> Tomasz Figa gets merged.
>>>>
>>>> [1]: mfd: syscon: Decouple syscon interface from syscon devices
>>>> https://lkml.org/lkml/2014/6/24/188
>>>
>>> That RFC patch had few comments from Arnd needed to be addressed, so it
>> needs a
>>> new revision.
>>>
>>> Pankaj, If I remember correctly, we had talked about this and the
>> conclusion was that
>>> you would take care of addressing the comments and sending new version of
>> the
>>> patch. Any update on this or have I missed something?
>>>
>>
>> Well, I don't think we concluded as such anything.
>> Since this patch needs to get in so that Exynos PMU and PM related changes
>> can go in,
>> I discussed with you saying that I am not able to understand about Arnd's
>> comments and
>> if possible and time permits I will look into it. Meanwhile I got busy with
>> some other
>> official work, so could not get time to look into it.
>
> Tomasz/Pankaj, could we please get some agreement on what needs to be
> done and who should do the pending work?
>
> syscon patch is blocking PMU cleanup patches which in turn are blocking
> PMU support additions for new SoCs (Exynos5420/5800 and Exynos3250 PMU
> patches).
Leaving alone the matter who is going to take care of it for now, the
remaining work to do is to further decouple syscon from struct device,
which means providing of_ API to register a syscon provider on a device
tree node even before driver model is available yet.
I believe it should be quite straightforward on top of my RFC and should
require only saving syscon's of_node directly in syscon struct, adding
appropriate API and extending the look-up loops to handle cases when
syscon's dev is NULL.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
@ 2014-08-19 14:30 ` Tomasz Figa
0 siblings, 0 replies; 35+ messages in thread
From: Tomasz Figa @ 2014-08-19 14:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi Bart,
On 18.08.2014 19:42, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> On Monday, July 28, 2014 08:40:52 AM Pankaj Dubey wrote:
>> Hi Tomasz,
>>
>> On Friday, July 25, 2014 Tomasz Figa wrote:
>>
>>> To: Pankaj Dubey; 'Kukjin Kim'; linux-arm-kernel at lists.infradead.org;
>> linux-
>>> samsung-soc at vger.kernel.org; linux-kernel at vger.kernel.org
>>> Cc: linux at arm.linux.org.uk; t.figa at samsung.com; vikas.sajjan at samsung.com;
>>> joshi at samsung.com; naushad at samsung.com; thomas.ab at samsung.com;
>>> chow.kim at samsung.com
>>> Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for
>>> Exynos PMU
>>>
>>> Hi Pankaj, Kukjin,
>>>
>>> On 25.07.2014 07:32, Pankaj Dubey wrote:
>>>> Hi Kukjin,
>>>>
>>>> On Friday, July 25, 2014 Kukjin Kim wrote:
>>>
>>> [snip]
>>>
>>>>>>
>>>>> Looks good to me, will apply this and 4/4.
>>>>>
>>>>
>>>> We need to hold these two patches until dependent patch [1] from
>>>> Tomasz Figa gets merged.
>>>>
>>>> [1]: mfd: syscon: Decouple syscon interface from syscon devices
>>>> https://lkml.org/lkml/2014/6/24/188
>>>
>>> That RFC patch had few comments from Arnd needed to be addressed, so it
>> needs a
>>> new revision.
>>>
>>> Pankaj, If I remember correctly, we had talked about this and the
>> conclusion was that
>>> you would take care of addressing the comments and sending new version of
>> the
>>> patch. Any update on this or have I missed something?
>>>
>>
>> Well, I don't think we concluded as such anything.
>> Since this patch needs to get in so that Exynos PMU and PM related changes
>> can go in,
>> I discussed with you saying that I am not able to understand about Arnd's
>> comments and
>> if possible and time permits I will look into it. Meanwhile I got busy with
>> some other
>> official work, so could not get time to look into it.
>
> Tomasz/Pankaj, could we please get some agreement on what needs to be
> done and who should do the pending work?
>
> syscon patch is blocking PMU cleanup patches which in turn are blocking
> PMU support additions for new SoCs (Exynos5420/5800 and Exynos3250 PMU
> patches).
Leaving alone the matter who is going to take care of it for now, the
remaining work to do is to further decouple syscon from struct device,
which means providing of_ API to register a syscon provider on a device
tree node even before driver model is available yet.
I believe it should be quite straightforward on top of my RFC and should
require only saving syscon's of_node directly in syscon struct, adding
appropriate API and extending the look-up loops to handle cases when
syscon's dev is NULL.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
2014-08-19 14:30 ` Tomasz Figa
@ 2014-08-21 14:07 ` Pankaj Dubey
-1 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-08-21 14:07 UTC (permalink / raw)
To: 'Tomasz Figa', 'Bartlomiej Zolnierkiewicz',
'Arnd Bergmann', 'Lee Jones'
Cc: linux-arm-kernel, linux-samsung-soc, linux-kernel, linux, t.figa,
vikas.sajjan, joshi, naushad, thomas.ab, chow.kim,
'Kukjin Kim',
PRASHANTH GODREHAL
+Arnd, Lee Jones
Hi Tomasz,
On Tuesday, August 19, 2014 Tomasz Figa wrote:
>
> Hi Bart,
>
> On 18.08.2014 19:42, Bartlomiej Zolnierkiewicz wrote:
> >
> > Hi,
> >
> > On Monday, July 28, 2014 08:40:52 AM Pankaj Dubey wrote:
> >> Hi Tomasz,
> >>
> >> On Friday, July 25, 2014 Tomasz Figa wrote:
> >>
> >>> To: Pankaj Dubey; 'Kukjin Kim';
> >>> linux-arm-kernel@lists.infradead.org;
> >> linux-
> >>> samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org
> >>> Cc: linux@arm.linux.org.uk; t.figa@samsung.com;
> >>> vikas.sajjan@samsung.com; joshi@samsung.com; naushad@samsung.com;
> >>> thomas.ab@samsung.com; chow.kim@samsung.com
> >>> Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support
> >>> for Exynos PMU
> >>>
> >>> Hi Pankaj, Kukjin,
> >>>
> >>> On 25.07.2014 07:32, Pankaj Dubey wrote:
> >>>> Hi Kukjin,
> >>>>
> >>>> On Friday, July 25, 2014 Kukjin Kim wrote:
> >>>
> >>> [snip]
> >>>
> >>>>>>
> >>>>> Looks good to me, will apply this and 4/4.
> >>>>>
> >>>>
> >>>> We need to hold these two patches until dependent patch [1] from
> >>>> Tomasz Figa gets merged.
> >>>>
> >>>> [1]: mfd: syscon: Decouple syscon interface from syscon devices
> >>>> https://lkml.org/lkml/2014/6/24/188
> >>>
> >>> That RFC patch had few comments from Arnd needed to be addressed, so
> >>> it
> >> needs a
> >>> new revision.
> >>>
> >>> Pankaj, If I remember correctly, we had talked about this and the
> >> conclusion was that
> >>> you would take care of addressing the comments and sending new
> >>> version of
> >> the
> >>> patch. Any update on this or have I missed something?
> >>>
> >>
> >> Well, I don't think we concluded as such anything.
> >> Since this patch needs to get in so that Exynos PMU and PM related
> >> changes can go in, I discussed with you saying that I am not able to
> >> understand about Arnd's comments and if possible and time permits I
> >> will look into it. Meanwhile I got busy with some other official
> >> work, so could not get time to look into it.
> >
> > Tomasz/Pankaj, could we please get some agreement on what needs to be
> > done and who should do the pending work?
> >
> > syscon patch is blocking PMU cleanup patches which in turn are
> > blocking PMU support additions for new SoCs (Exynos5420/5800 and
> > Exynos3250 PMU patches).
>
> Leaving alone the matter who is going to take care of it for now, the
remaining work
> to do is to further decouple syscon from struct device, which means
providing of_
> API to register a syscon provider on a device tree node even before driver
model is
> available yet.
>
As per Arnd's comment on your RFC patch he mentioned -
"I believe the part you are missing is that with the approach I suggested,
there would be no registration function at all."
I think he is not in favor of adding such registration function at all. So
do you think
adding such function will really solve the problem?
Further even Lee Jones agreed to Arnd's point of making syscon independent
of device,
but he also mentioned that it can be done in subsequent patch.
So in IMHO, your RFC patch can be taken as is, and any further improvement
suggested
by Arnd can be done in subsequent patches, because as I can see in 3.17-rc1
still
has user of syscon_regmap_lookup_by_pdevname (clps711x.c) so we can't
completely
make it independent of platform_device as of now and also the changes
required
as per Arnd's suggestions requires considerable effort and time.
> I believe it should be quite straightforward on top of my RFC and should
require only
> saving syscon's of_node directly in syscon struct, adding appropriate API
and
> extending the look-up loops to handle cases when syscon's dev is NULL.
>
> Best regards,
> Tomasz
Thanks,
Pankaj Dubey
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
@ 2014-08-21 14:07 ` Pankaj Dubey
0 siblings, 0 replies; 35+ messages in thread
From: Pankaj Dubey @ 2014-08-21 14:07 UTC (permalink / raw)
To: linux-arm-kernel
+Arnd, Lee Jones
Hi Tomasz,
On Tuesday, August 19, 2014 Tomasz Figa wrote:
>
> Hi Bart,
>
> On 18.08.2014 19:42, Bartlomiej Zolnierkiewicz wrote:
> >
> > Hi,
> >
> > On Monday, July 28, 2014 08:40:52 AM Pankaj Dubey wrote:
> >> Hi Tomasz,
> >>
> >> On Friday, July 25, 2014 Tomasz Figa wrote:
> >>
> >>> To: Pankaj Dubey; 'Kukjin Kim';
> >>> linux-arm-kernel at lists.infradead.org;
> >> linux-
> >>> samsung-soc at vger.kernel.org; linux-kernel at vger.kernel.org
> >>> Cc: linux at arm.linux.org.uk; t.figa at samsung.com;
> >>> vikas.sajjan at samsung.com; joshi at samsung.com; naushad at samsung.com;
> >>> thomas.ab at samsung.com; chow.kim at samsung.com
> >>> Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support
> >>> for Exynos PMU
> >>>
> >>> Hi Pankaj, Kukjin,
> >>>
> >>> On 25.07.2014 07:32, Pankaj Dubey wrote:
> >>>> Hi Kukjin,
> >>>>
> >>>> On Friday, July 25, 2014 Kukjin Kim wrote:
> >>>
> >>> [snip]
> >>>
> >>>>>>
> >>>>> Looks good to me, will apply this and 4/4.
> >>>>>
> >>>>
> >>>> We need to hold these two patches until dependent patch [1] from
> >>>> Tomasz Figa gets merged.
> >>>>
> >>>> [1]: mfd: syscon: Decouple syscon interface from syscon devices
> >>>> https://lkml.org/lkml/2014/6/24/188
> >>>
> >>> That RFC patch had few comments from Arnd needed to be addressed, so
> >>> it
> >> needs a
> >>> new revision.
> >>>
> >>> Pankaj, If I remember correctly, we had talked about this and the
> >> conclusion was that
> >>> you would take care of addressing the comments and sending new
> >>> version of
> >> the
> >>> patch. Any update on this or have I missed something?
> >>>
> >>
> >> Well, I don't think we concluded as such anything.
> >> Since this patch needs to get in so that Exynos PMU and PM related
> >> changes can go in, I discussed with you saying that I am not able to
> >> understand about Arnd's comments and if possible and time permits I
> >> will look into it. Meanwhile I got busy with some other official
> >> work, so could not get time to look into it.
> >
> > Tomasz/Pankaj, could we please get some agreement on what needs to be
> > done and who should do the pending work?
> >
> > syscon patch is blocking PMU cleanup patches which in turn are
> > blocking PMU support additions for new SoCs (Exynos5420/5800 and
> > Exynos3250 PMU patches).
>
> Leaving alone the matter who is going to take care of it for now, the
remaining work
> to do is to further decouple syscon from struct device, which means
providing of_
> API to register a syscon provider on a device tree node even before driver
model is
> available yet.
>
As per Arnd's comment on your RFC patch he mentioned -
"I believe the part you are missing is that with the approach I suggested,
there would be no registration function at all."
I think he is not in favor of adding such registration function at all. So
do you think
adding such function will really solve the problem?
Further even Lee Jones agreed to Arnd's point of making syscon independent
of device,
but he also mentioned that it can be done in subsequent patch.
So in IMHO, your RFC patch can be taken as is, and any further improvement
suggested
by Arnd can be done in subsequent patches, because as I can see in 3.17-rc1
still
has user of syscon_regmap_lookup_by_pdevname (clps711x.c) so we can't
completely
make it independent of platform_device as of now and also the changes
required
as per Arnd's suggestions requires considerable effort and time.
> I believe it should be quite straightforward on top of my RFC and should
require only
> saving syscon's of_node directly in syscon struct, adding appropriate API
and
> extending the look-up loops to handle cases when syscon's dev is NULL.
>
> Best regards,
> Tomasz
Thanks,
Pankaj Dubey
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
2014-08-21 14:07 ` Pankaj Dubey
@ 2014-08-21 15:59 ` Tomasz Figa
-1 siblings, 0 replies; 35+ messages in thread
From: Tomasz Figa @ 2014-08-21 15:59 UTC (permalink / raw)
To: Pankaj Dubey, 'Bartlomiej Zolnierkiewicz',
'Arnd Bergmann', 'Lee Jones'
Cc: linux-arm-kernel, linux-samsung-soc, linux-kernel, linux, t.figa,
vikas.sajjan, joshi, naushad, thomas.ab, chow.kim,
'Kukjin Kim',
PRASHANTH GODREHAL
On 21.08.2014 16:07, Pankaj Dubey wrote:
> +Arnd, Lee Jones
>
> Hi Tomasz,
>
> On Tuesday, August 19, 2014 Tomasz Figa wrote:
>
>>
>> Hi Bart,
>>
>> On 18.08.2014 19:42, Bartlomiej Zolnierkiewicz wrote:
>>>
>>> Hi,
>>>
>>> On Monday, July 28, 2014 08:40:52 AM Pankaj Dubey wrote:
>>>> Hi Tomasz,
>>>>
>>>> On Friday, July 25, 2014 Tomasz Figa wrote:
>>>>
>>>>> To: Pankaj Dubey; 'Kukjin Kim';
>>>>> linux-arm-kernel@lists.infradead.org;
>>>> linux-
>>>>> samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org
>>>>> Cc: linux@arm.linux.org.uk; t.figa@samsung.com;
>>>>> vikas.sajjan@samsung.com; joshi@samsung.com; naushad@samsung.com;
>>>>> thomas.ab@samsung.com; chow.kim@samsung.com
>>>>> Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support
>>>>> for Exynos PMU
>>>>>
>>>>> Hi Pankaj, Kukjin,
>>>>>
>>>>> On 25.07.2014 07:32, Pankaj Dubey wrote:
>>>>>> Hi Kukjin,
>>>>>>
>>>>>> On Friday, July 25, 2014 Kukjin Kim wrote:
>>>>>
>>>>> [snip]
>>>>>
>>>>>>>>
>>>>>>> Looks good to me, will apply this and 4/4.
>>>>>>>
>>>>>>
>>>>>> We need to hold these two patches until dependent patch [1] from
>>>>>> Tomasz Figa gets merged.
>>>>>>
>>>>>> [1]: mfd: syscon: Decouple syscon interface from syscon devices
>>>>>> https://lkml.org/lkml/2014/6/24/188
>>>>>
>>>>> That RFC patch had few comments from Arnd needed to be addressed, so
>>>>> it
>>>> needs a
>>>>> new revision.
>>>>>
>>>>> Pankaj, If I remember correctly, we had talked about this and the
>>>> conclusion was that
>>>>> you would take care of addressing the comments and sending new
>>>>> version of
>>>> the
>>>>> patch. Any update on this or have I missed something?
>>>>>
>>>>
>>>> Well, I don't think we concluded as such anything.
>>>> Since this patch needs to get in so that Exynos PMU and PM related
>>>> changes can go in, I discussed with you saying that I am not able to
>>>> understand about Arnd's comments and if possible and time permits I
>>>> will look into it. Meanwhile I got busy with some other official
>>>> work, so could not get time to look into it.
>>>
>>> Tomasz/Pankaj, could we please get some agreement on what needs to be
>>> done and who should do the pending work?
>>>
>>> syscon patch is blocking PMU cleanup patches which in turn are
>>> blocking PMU support additions for new SoCs (Exynos5420/5800 and
>>> Exynos3250 PMU patches).
>>
>> Leaving alone the matter who is going to take care of it for now, the
> remaining work
>> to do is to further decouple syscon from struct device, which means
> providing of_
>> API to register a syscon provider on a device tree node even before driver
> model is
>> available yet.
>>
>
> As per Arnd's comment on your RFC patch he mentioned -
> "I believe the part you are missing is that with the approach I suggested,
> there would be no registration function at all."
>
> I think he is not in favor of adding such registration function at all. So
> do you think
> adding such function will really solve the problem?
>
> Further even Lee Jones agreed to Arnd's point of making syscon independent
> of device,
> but he also mentioned that it can be done in subsequent patch.
Let's look again at the original thread then...
I believe Lee agreed with my proposed solution or at least he quoted my
e-mail and pointed that further work addressing Arnd's comments could be
done in follow up patches. I also think that we should rather make one
step as a time, especially this patch is required for further clean-up
of Exynos.
However there was also a reply from Michal Simek, which pointed out that
even with my patch the syscon is still bound to driver model and for his
use case he would need a purely OF-based version of the API. That's why
I think my patch should be re-spun with changes I mentioned in my
previous message in this thread.
>
> So in IMHO, your RFC patch can be taken as is, and any further improvement
> suggested
> by Arnd can be done in subsequent patches, because as I can see in 3.17-rc1
> still
> has user of syscon_regmap_lookup_by_pdevname (clps711x.c) so we can't
> completely
> make it independent of platform_device as of now and also the changes
> required
> as per Arnd's suggestions requires considerable effort and time.
Agreed. However we can still provide OF-only syscon registration
function and modify look-up functions to allow syscons without struct
device pointer, just with OF node.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU
@ 2014-08-21 15:59 ` Tomasz Figa
0 siblings, 0 replies; 35+ messages in thread
From: Tomasz Figa @ 2014-08-21 15:59 UTC (permalink / raw)
To: linux-arm-kernel
On 21.08.2014 16:07, Pankaj Dubey wrote:
> +Arnd, Lee Jones
>
> Hi Tomasz,
>
> On Tuesday, August 19, 2014 Tomasz Figa wrote:
>
>>
>> Hi Bart,
>>
>> On 18.08.2014 19:42, Bartlomiej Zolnierkiewicz wrote:
>>>
>>> Hi,
>>>
>>> On Monday, July 28, 2014 08:40:52 AM Pankaj Dubey wrote:
>>>> Hi Tomasz,
>>>>
>>>> On Friday, July 25, 2014 Tomasz Figa wrote:
>>>>
>>>>> To: Pankaj Dubey; 'Kukjin Kim';
>>>>> linux-arm-kernel at lists.infradead.org;
>>>> linux-
>>>>> samsung-soc at vger.kernel.org; linux-kernel at vger.kernel.org
>>>>> Cc: linux at arm.linux.org.uk; t.figa at samsung.com;
>>>>> vikas.sajjan at samsung.com; joshi at samsung.com; naushad at samsung.com;
>>>>> thomas.ab at samsung.com; chow.kim at samsung.com
>>>>> Subject: Re: [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support
>>>>> for Exynos PMU
>>>>>
>>>>> Hi Pankaj, Kukjin,
>>>>>
>>>>> On 25.07.2014 07:32, Pankaj Dubey wrote:
>>>>>> Hi Kukjin,
>>>>>>
>>>>>> On Friday, July 25, 2014 Kukjin Kim wrote:
>>>>>
>>>>> [snip]
>>>>>
>>>>>>>>
>>>>>>> Looks good to me, will apply this and 4/4.
>>>>>>>
>>>>>>
>>>>>> We need to hold these two patches until dependent patch [1] from
>>>>>> Tomasz Figa gets merged.
>>>>>>
>>>>>> [1]: mfd: syscon: Decouple syscon interface from syscon devices
>>>>>> https://lkml.org/lkml/2014/6/24/188
>>>>>
>>>>> That RFC patch had few comments from Arnd needed to be addressed, so
>>>>> it
>>>> needs a
>>>>> new revision.
>>>>>
>>>>> Pankaj, If I remember correctly, we had talked about this and the
>>>> conclusion was that
>>>>> you would take care of addressing the comments and sending new
>>>>> version of
>>>> the
>>>>> patch. Any update on this or have I missed something?
>>>>>
>>>>
>>>> Well, I don't think we concluded as such anything.
>>>> Since this patch needs to get in so that Exynos PMU and PM related
>>>> changes can go in, I discussed with you saying that I am not able to
>>>> understand about Arnd's comments and if possible and time permits I
>>>> will look into it. Meanwhile I got busy with some other official
>>>> work, so could not get time to look into it.
>>>
>>> Tomasz/Pankaj, could we please get some agreement on what needs to be
>>> done and who should do the pending work?
>>>
>>> syscon patch is blocking PMU cleanup patches which in turn are
>>> blocking PMU support additions for new SoCs (Exynos5420/5800 and
>>> Exynos3250 PMU patches).
>>
>> Leaving alone the matter who is going to take care of it for now, the
> remaining work
>> to do is to further decouple syscon from struct device, which means
> providing of_
>> API to register a syscon provider on a device tree node even before driver
> model is
>> available yet.
>>
>
> As per Arnd's comment on your RFC patch he mentioned -
> "I believe the part you are missing is that with the approach I suggested,
> there would be no registration function at all."
>
> I think he is not in favor of adding such registration function at all. So
> do you think
> adding such function will really solve the problem?
>
> Further even Lee Jones agreed to Arnd's point of making syscon independent
> of device,
> but he also mentioned that it can be done in subsequent patch.
Let's look again at the original thread then...
I believe Lee agreed with my proposed solution or at least he quoted my
e-mail and pointed that further work addressing Arnd's comments could be
done in follow up patches. I also think that we should rather make one
step as a time, especially this patch is required for further clean-up
of Exynos.
However there was also a reply from Michal Simek, which pointed out that
even with my patch the syscon is still bound to driver model and for his
use case he would need a purely OF-based version of the API. That's why
I think my patch should be re-spun with changes I mentioned in my
previous message in this thread.
>
> So in IMHO, your RFC patch can be taken as is, and any further improvement
> suggested
> by Arnd can be done in subsequent patches, because as I can see in 3.17-rc1
> still
> has user of syscon_regmap_lookup_by_pdevname (clps711x.c) so we can't
> completely
> make it independent of platform_device as of now and also the changes
> required
> as per Arnd's suggestions requires considerable effort and time.
Agreed. However we can still provide OF-only syscon registration
function and modify look-up functions to allow syscons without struct
device pointer, just with OF node.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2014-08-21 15:59 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-07-09 4:00 [PATCH v7 0/4] ARM: Exynos: PMU cleanup and refactoring for using DT Pankaj Dubey
2014-07-09 4:00 ` Pankaj Dubey
2014-07-09 4:00 ` [PATCH v7 1/4] ARM: EXYNOS: Add support for mapping PMU base address via DT Pankaj Dubey
2014-07-09 4:00 ` Pankaj Dubey
2014-07-10 13:49 ` Kukjin Kim
2014-07-10 13:49 ` Kukjin Kim
2014-07-27 3:33 ` Andreas Färber
2014-07-27 3:33 ` Andreas Färber
2014-07-09 4:00 ` [PATCH v7 2/4] ARM: EXYNOS: Refactored code for using PMU " Pankaj Dubey
2014-07-09 4:00 ` Pankaj Dubey
2014-07-10 13:52 ` Kukjin Kim
2014-07-10 13:52 ` Kukjin Kim
2014-07-09 4:00 ` [PATCH v7 3/4] ARM: EXYNOS: Add platform driver support for Exynos PMU Pankaj Dubey
2014-07-09 4:00 ` Pankaj Dubey
2014-07-25 4:04 ` Kukjin Kim
2014-07-25 4:04 ` Kukjin Kim
2014-07-25 5:32 ` Pankaj Dubey
2014-07-25 5:32 ` Pankaj Dubey
2014-07-25 11:00 ` Tomasz Figa
2014-07-25 11:00 ` Tomasz Figa
2014-07-28 3:10 ` Pankaj Dubey
2014-07-28 3:10 ` Pankaj Dubey
2014-08-18 17:42 ` Bartlomiej Zolnierkiewicz
2014-08-18 17:42 ` Bartlomiej Zolnierkiewicz
2014-08-19 14:30 ` Tomasz Figa
2014-08-19 14:30 ` Tomasz Figa
2014-08-21 14:07 ` Pankaj Dubey
2014-08-21 14:07 ` Pankaj Dubey
2014-08-21 15:59 ` Tomasz Figa
2014-08-21 15:59 ` Tomasz Figa
2014-07-09 4:00 ` [PATCH v7 4/4] ARM: EXYNOS: Move PMU specific definitions from common.h Pankaj Dubey
2014-07-09 4:00 ` Pankaj Dubey
2014-07-11 6:10 ` [PATCH v7 0/4] ARM: Exynos: PMU cleanup and refactoring for using DT Naveen Krishna Ch
2014-07-11 6:10 ` Naveen Krishna Ch
2014-07-11 6:10 ` Naveen Krishna Ch
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