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From: Olav Haugan <ohaugan@codeaurora.org>
To: will.deacon@arm.com
Cc: mitchelh@codeaurora.org, iommu@lists.linux-foundation.org,
	linux-arm-kernel@lists.infradead.org,
	linux-arm-msm@vger.kernel.org,
	Olav Haugan <ohaugan@codeaurora.org>
Subject: [PATCH v2 0/2] arm-smmu fixes for CBn_TCR and S2CR/SMR programming
Date: Mon,  4 Aug 2014 11:01:01 -0700	[thread overview]
Message-ID: <1407175263-10699-1-git-send-email-ohaugan@codeaurora.org> (raw)

Here are a couple fixes for the arm smmu driver. The first one deals with
ensuring that we program CBn_TCR correctly when we are programming a stage-1
context bank.
The second patch ensures that SMR registers are not touched when stream
matchign is not supported by the hardware. When stream id matching is not
supported by the hardware the SMR registers does not exists. However, even
if they are UNK/SBZP we prefer not to write to more registers than needed.

v1 -> v2:
* Fixed so that SL0 is programed for SMMUv1 hardware also
* Rebased onto Will's iommu/pci branch which only left one issue to fix
  for the second patch.

Olav Haugan (2):
  iommu/arm-smmu: Fix programming of SMMU_CBn_TCR for stage 1
  iommu/arm-smmu: Do not access non-existing SMR registers

 drivers/iommu/arm-smmu.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

WARNING: multiple messages have this Message-ID
From: ohaugan@codeaurora.org (Olav Haugan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 0/2] arm-smmu fixes for CBn_TCR and S2CR/SMR programming
Date: Mon,  4 Aug 2014 11:01:01 -0700	[thread overview]
Message-ID: <1407175263-10699-1-git-send-email-ohaugan@codeaurora.org> (raw)

Here are a couple fixes for the arm smmu driver. The first one deals with
ensuring that we program CBn_TCR correctly when we are programming a stage-1
context bank.
The second patch ensures that SMR registers are not touched when stream
matchign is not supported by the hardware. When stream id matching is not
supported by the hardware the SMR registers does not exists. However, even
if they are UNK/SBZP we prefer not to write to more registers than needed.

v1 -> v2:
* Fixed so that SL0 is programed for SMMUv1 hardware also
* Rebased onto Will's iommu/pci branch which only left one issue to fix
  for the second patch.

Olav Haugan (2):
  iommu/arm-smmu: Fix programming of SMMU_CBn_TCR for stage 1
  iommu/arm-smmu: Do not access non-existing SMR registers

 drivers/iommu/arm-smmu.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

             reply	other threads:[~2014-08-04 18:01 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-04 18:01 Olav Haugan [this message]
2014-08-04 18:01 ` Olav Haugan
2014-08-04 18:01 ` [PATCH v2 1/2] iommu/arm-smmu: Fix programming of SMMU_CBn_TCR for stage 1 Olav Haugan
2014-08-04 18:01   ` Olav Haugan
2014-08-04 18:01 ` [PATCH v2 2/2] iommu/arm-smmu: Do not access non-existing SMR registers Olav Haugan
2014-08-04 18:01   ` Olav Haugan
2014-08-06 10:19   ` Will Deacon
2014-08-06 10:19     ` Will Deacon
2014-08-06 16:44     ` Olav Haugan
2014-08-06 16:44       ` Olav Haugan
     [not found]       ` <53E25B76.6090208-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2014-08-06 17:35         ` Will Deacon
2014-08-06 17:35           ` Will Deacon
     [not found]           ` <20140806173518.GG25953-5wv7dgnIgG8@public.gmane.org>
2014-08-06 23:34             ` Olav Haugan
2014-08-06 23:34               ` Olav Haugan
2014-08-07  9:22               ` Will Deacon
2014-08-07  9:22                 ` Will Deacon
     [not found]                 ` <20140807092254.GH13703-5wv7dgnIgG8@public.gmane.org>
2014-08-08 18:51                   ` Olav Haugan
2014-08-08 18:51                     ` Olav Haugan

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