From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: [PATCH 06/15] drm/i915: Refactor the physical and virtual page hws setup Date: Tue, 5 Aug 2014 07:51:17 -0700 Message-ID: <1407250286-1801-7-git-send-email-rodrigo.vivi@intel.com> References: <1407250286-1801-1-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 53AE96E4E3 for ; Tue, 5 Aug 2014 14:50:52 -0700 (PDT) In-Reply-To: <1407250286-1801-1-git-send-email-rodrigo.vivi@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org From: Chris Wilson We duplicated the legacy physical HWS setup routine for no good reason. Combine it with the more recent virtual HWS setup for simplicity. Signed-off-by: Chris Wilson Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_dma.c | 16 +------ drivers/gpu/drm/i915/intel_ringbuffer.c | 81 ++++++++++++++++----------------- 2 files changed, 39 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 2e7f03a..f76d2bf 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -104,17 +104,6 @@ void i915_update_dri1_breadcrumb(struct drm_device *dev) } } -static void i915_write_hws_pga(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - u32 addr; - - addr = dev_priv->status_page_dmah->busaddr; - if (INTEL_INFO(dev)->gen >= 4) - addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; - I915_WRITE(HWS_PGA, addr); -} - /** * Frees the hardware status page, whether it's a physical address or a virtual * address set up by the X Server. @@ -255,10 +244,7 @@ static int i915_dma_resume(struct drm_device *dev) } DRM_DEBUG_DRIVER("hw status page @ %p\n", ring->status_page.page_addr); - if (ring->status_page.gfx_addr != 0) - intel_ring_setup_status_page(ring); - else - i915_write_hws_pga(dev); + intel_ring_setup_status_page(ring); DRM_DEBUG_DRIVER("Enabled hardware status page\n"); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b3d8f76..b7894d1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -443,17 +443,6 @@ u64 intel_ring_get_active_head(struct intel_engine_cs *ring) return acthd; } -static void ring_setup_phys_status_page(struct intel_engine_cs *ring) -{ - struct drm_i915_private *dev_priv = ring->dev->dev_private; - u32 addr; - - addr = dev_priv->status_page_dmah->busaddr; - if (INTEL_INFO(ring->dev)->gen >= 4) - addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; - I915_WRITE(HWS_PGA, addr); -} - static bool stop_ring(struct intel_engine_cs *ring) { struct drm_i915_private *dev_priv = to_i915(ring->dev); @@ -511,10 +500,7 @@ static int init_ring_common(struct intel_engine_cs *ring) } } - if (I915_NEED_GFX_HWS(dev)) - intel_ring_setup_status_page(ring); - else - ring_setup_phys_status_page(ring); + intel_ring_setup_status_page(ring); /* Initialize the ring. This must happen _after_ we've cleared the ring * registers with the above sequence (the readback of the HEAD registers @@ -1101,39 +1087,48 @@ void intel_ring_setup_status_page(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; struct drm_i915_private *dev_priv = ring->dev->dev_private; - u32 mmio = 0; + u32 mmio, addr; - /* The ring status page addresses are no longer next to the rest of - * the ring registers as of gen7. - */ - if (IS_GEN7(dev)) { - switch (ring->id) { - case RCS: - mmio = RENDER_HWS_PGA_GEN7; - break; - case BCS: - mmio = BLT_HWS_PGA_GEN7; - break; - /* - * VCS2 actually doesn't exist on Gen7. Only shut up - * gcc switch check warning + if (!I915_NEED_GFX_HWS(dev)) { + addr = dev_priv->status_page_dmah->busaddr; + if (INTEL_INFO(ring->dev)->gen >= 4) + addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; + mmio = HWS_PGA; + } else { + addr = ring->status_page.gfx_addr; + /* The ring status page addresses are no longer next to the rest of + * the ring registers as of gen7. */ - case VCS2: - case VCS: - mmio = BSD_HWS_PGA_GEN7; - break; - case VECS: - mmio = VEBOX_HWS_PGA_GEN7; - break; + if (IS_GEN7(dev)) { + switch (ring->id) { + default: + case RCS: + mmio = RENDER_HWS_PGA_GEN7; + break; + case BCS: + mmio = BLT_HWS_PGA_GEN7; + break; + /* + * VCS2 actually doesn't exist on Gen7. Only shut up + * gcc switch check warning + */ + case VCS2: + case VCS: + mmio = BSD_HWS_PGA_GEN7; + break; + case VECS: + mmio = VEBOX_HWS_PGA_GEN7; + break; + } + } else if (IS_GEN6(ring->dev)) { + mmio = RING_HWS_PGA_GEN6(ring->mmio_base); + } else { + /* XXX: gen8 returns to sanity */ + mmio = RING_HWS_PGA(ring->mmio_base); } - } else if (IS_GEN6(ring->dev)) { - mmio = RING_HWS_PGA_GEN6(ring->mmio_base); - } else { - /* XXX: gen8 returns to sanity */ - mmio = RING_HWS_PGA(ring->mmio_base); } - I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); + I915_WRITE(mmio, addr); POSTING_READ(mmio); /* -- 1.9.3