From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49227) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKm6x-0001zm-7T for qemu-devel@nongnu.org; Fri, 22 Aug 2014 06:30:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XKm6p-00049E-PA for qemu-devel@nongnu.org; Fri, 22 Aug 2014 06:30:23 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:57019) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKm6p-00047W-Hv for qemu-devel@nongnu.org; Fri, 22 Aug 2014 06:30:15 -0400 From: Fabian Aggeler Date: Fri, 22 Aug 2014 12:29:46 +0200 Message-ID: <1408703392-23893-10-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1408703392-23893-1-git-send-email-aggelerf@ethz.ch> References: <1408703392-23893-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 09/15] hw/intc/arm_gic: Implement Non-secure view of RPR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, greg.bellows@linaro.org, christoffer.dall@linaro.org, edgar.iglesias@gmail.com For GICs with Security Extensions Non-secure reads have a restricted view on the current running priority. Signed-off-by: Fabian Aggeler --- hw/intc/arm_gic.c | 17 ++++++++++++++++- hw/intc/gic_internal.h | 1 + 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 57021fd..473b8f4 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -285,6 +285,21 @@ void gic_set_cpu_control(GICState *s, int cpu, uint32_t value) } } +uint8_t gic_get_running_priority(GICState *s, int cpu) +{ + if (s->security_extn && ns_access()) { + if (s->running_priority[cpu] & 0x80) { + /* Running priority in upper half, return Non-secure view */ + return s->running_priority[cpu] << 1; + } else { + /* Running priority in lower half, RAZ */ + return 0; + } + } else { + return s->running_priority[cpu]; + } +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -801,7 +816,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x0c: /* Acknowledge */ return gic_acknowledge_irq(s, cpu); case 0x14: /* Running Priority */ - return s->running_priority[cpu]; + return gic_get_running_priority(s, cpu); case 0x18: /* Highest Pending Interrupt */ return s->current_pending[cpu]; case 0x1c: /* Aliased Binary Point */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index e9814f4..433d75e 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -78,6 +78,7 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq); void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); uint32_t gic_get_cpu_control(GICState *s, int cpu); void gic_set_cpu_control(GICState *s, int cpu, uint32_t value); +uint8_t gic_get_running_priority(GICState *s, int cpu); static inline bool gic_test_pending(GICState *s, int irq, int cm) -- 1.8.3.2