From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49235) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKm6x-0001zn-CO for qemu-devel@nongnu.org; Fri, 22 Aug 2014 06:30:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XKm6n-00047s-Bs for qemu-devel@nongnu.org; Fri, 22 Aug 2014 06:30:23 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:10447) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKm6n-00047S-5e for qemu-devel@nongnu.org; Fri, 22 Aug 2014 06:30:13 -0400 From: Fabian Aggeler Date: Fri, 22 Aug 2014 12:29:38 +0200 Message-ID: <1408703392-23893-2-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1408703392-23893-1-git-send-email-aggelerf@ethz.ch> References: <1408703392-23893-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 01/15] hw/intc/arm_gic: Request FIQ sources List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, greg.bellows@linaro.org, christoffer.dall@linaro.org, edgar.iglesias@gmail.com Preparing for FIQ lines from GIC to CPUs, which is needed for GIC Security Extensions. Signed-off-by: Fabian Aggeler --- hw/intc/arm_gic.c | 3 +++ include/hw/intc/arm_gic_common.h | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1532ef9..b27bd0e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -786,6 +786,9 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq) for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(sbd, &s->parent_irq[i]); } + for (i = 0; i < NUM_CPU(s); i++) { + sysbus_init_irq(sbd, &s->parent_fiq[i]); + } memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, "gic_dist", 0x1000); } diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index f6887ed..01c6f24 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -50,6 +50,7 @@ typedef struct GICState { /*< public >*/ qemu_irq parent_irq[GIC_NCPU]; + qemu_irq parent_fiq[GIC_NCPU]; bool enabled; bool cpu_enabled[GIC_NCPU]; -- 1.8.3.2