[Qemu-devel] [PATCH 04/15] hw/intc/arm_gic: Add ns_access() function

From: Fabian Aggeler <aggelerf@ethz.ch>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, greg.bellows@linaro.org,
	christoffer.dall@linaro.org, edgar.iglesias@gmail.com
Subject: [Qemu-devel] [PATCH 04/15] hw/intc/arm_gic: Add ns_access() function
Date: Fri, 22 Aug 2014 12:29:41 +0200	[thread overview]
Message-ID: <1408703392-23893-5-git-send-email-aggelerf@ethz.ch> (raw)
In-Reply-To: <1408703392-23893-1-git-send-email-aggelerf@ethz.ch>

Security Extensions for GICv1 and GICv2 use register banking
to provide transparent access to seperate Secure and Non-secure
copies of GIC configuration registers. This function will later
be replaced by code determining the security state of a read/write
access to a register.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
---
 hw/intc/arm_gic.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 75b5121..9b83af0 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -45,6 +45,13 @@ static inline int gic_get_current_cpu(GICState *s)
     return 0;
 }
 
+/* Security state of a read / write access */
+static inline bool ns_access(void)
+{
+    /* TODO: use actual security state */
+    return true;
+}
+
 /* TODO: Many places that call this routine could be optimized.  */
 /* Update interrupt status after enabled or pending bits have been changed.  */
 void gic_update(GICState *s)
-- 
1.8.3.2
